pll1_div           26 arch/sh/kernel/cpu/sh2a/clock-sh7264.c static unsigned int pll1_div;
pll1_div           43 arch/sh/kernel/cpu/sh2a/clock-sh7264.c 	unsigned long rate = clk->parent->rate / pll1_div;
pll1_div          139 arch/sh/kernel/cpu/sh2a/clock-sh7264.c 			pll1_div = 3;
pll1_div          141 arch/sh/kernel/cpu/sh2a/clock-sh7264.c 			pll1_div = 4;
pll1_div          143 arch/sh/kernel/cpu/sh2a/clock-sh7264.c 		pll1_div = 1;
pll1_div          575 drivers/clk/renesas/rcar-gen3-cpg.c 		div = cpg_pll_config->pll1_div;
pll1_div           60 drivers/clk/renesas/rcar-gen3-cpg.h 	u8 pll1_div;