pll10            12814 drivers/gpu/drm/i915/display/intel_display.c 	PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
pll10            1587 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	temp |= pll->state.hw_state.pll10;
pll10            1700 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	hw_state->pll10 = I915_READ(BXT_PORT_PLL(phy, ch, 10));
pll10            1701 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	hw_state->pll10 &= PORT_PLL_DCO_AMP_OVR_EN_H |
pll10            1855 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 	dpll_hw_state->pll10 =
pll10            1934 drivers/gpu/drm/i915/display/intel_dpll_mgr.c 		      hw_state->pll10,
pll10             195 drivers/gpu/drm/i915/display/intel_dpll_mgr.h 	u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12;