plane_states     6349 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 			dummy_updates[j].surface = status->plane_states[0];
plane_states     1281 drivers/gpu/drm/amd/display/dc/core/dc.c 					new_ctx->stream_status[i].plane_states[j]);
plane_states       60 drivers/gpu/drm/amd/display/dc/core/dc_debug.c 		const struct dc_plane_state *const *plane_states,
plane_states       67 drivers/gpu/drm/amd/display/dc/core/dc_debug.c 		const struct dc_plane_state *plane_state = plane_states[i];
plane_states     1301 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	stream_status->plane_states[stream_status->plane_count] = plane_state;
plane_states     1357 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		if (stream_status->plane_states[i] == plane_state) {
plane_states     1359 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 			dc_plane_state_release(stream_status->plane_states[i]);
plane_states     1373 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		stream_status->plane_states[i] = stream_status->plane_states[i + 1];
plane_states     1375 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	stream_status->plane_states[stream_status->plane_count] = NULL;
plane_states     1403 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		del_planes[i] = stream_status->plane_states[i];
plane_states     1431 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		if (!dc_add_plane_to_context(dc, stream, set[i].plane_states[j], context))
plane_states     1440 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		struct dc_plane_state * const *plane_states,
plane_states     1451 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		set.plane_states[i] = plane_states[i];
plane_states     2436 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 				context->stream_status[i].plane_states[j]);
plane_states     2473 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 				dst_ctx->stream_status[i].plane_states[j]);
plane_states      865 drivers/gpu/drm/amd/display/dc/dc.h 	struct dc_plane_state *plane_states[MAX_SURFACES];
plane_states       47 drivers/gpu/drm/amd/display/dc/dc_stream.h 	struct dc_plane_state *plane_states[MAX_SURFACE_NUM];
plane_states      332 drivers/gpu/drm/amd/display/dc/dc_stream.h 		struct dc_plane_state * const *plane_states,
plane_states      802 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 		if (context->stream_status[i].plane_states[0]->format
plane_states      988 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 				context->stream_status[i].plane_states[j];
plane_states      929 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 		if (context->stream_status[i].plane_states[0]->format
plane_states      836 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 		if (context->stream_status[i].plane_states[0]->format
plane_states     1164 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 				context->stream_status[i].plane_states[j];
plane_states       47 drivers/gpu/drm/amd/display/include/logger_interface.h 		const struct dc_plane_state *const *plane_states,
plane_states      488 drivers/gpu/drm/sun4i/sun4i_backend.c 	struct drm_plane_state *plane_states[SUN4I_BACKEND_NUM_LAYERS] = { 0 };
plane_states      539 drivers/gpu/drm/sun4i/sun4i_backend.c 		plane_states[plane_state->normalized_zpos] = plane_state;
plane_states      592 drivers/gpu/drm/sun4i/sun4i_backend.c 	    (plane_states[0]->fb->format->has_alpha ||
plane_states      593 drivers/gpu/drm/sun4i/sun4i_backend.c 	    (plane_states[0]->alpha != DRM_BLEND_ALPHA_OPAQUE)))
plane_states      597 drivers/gpu/drm/sun4i/sun4i_backend.c 		struct drm_plane_state *p_state = plane_states[i];