plane_res        2799 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 		data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.width);
plane_res        2801 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 		data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.height);
plane_res        2802 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 		data->h_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.h_taps);
plane_res        2803 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 		data->v_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.v_taps);
plane_res        2804 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 		data->h_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].plane_res.scl_data.ratios.horz.value);
plane_res        2805 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 		data->v_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].plane_res.scl_data.ratios.vert.value);
plane_res        2853 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 			data->src_height[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.viewport.height);
plane_res        2854 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 			data->src_width[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.viewport.width);
plane_res        2857 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 			data->h_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.taps.h_taps);
plane_res        2858 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 			data->v_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.taps.v_taps);
plane_res        2860 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 					pipe[i].bottom_pipe->plane_res.scl_data.ratios.horz.value);
plane_res        2862 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 					pipe[i].bottom_pipe->plane_res.scl_data.ratios.vert.value);
plane_res        2901 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 			data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.width);
plane_res        2903 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 			data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.height);
plane_res        2904 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 			data->h_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.h_taps);
plane_res        2905 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 			data->v_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.v_taps);
plane_res        2906 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 			data->h_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].plane_res.scl_data.ratios.horz.value);
plane_res        2907 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 			data->v_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].plane_res.scl_data.ratios.vert.value);
plane_res         313 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	if (pipe->plane_res.dpp->ctx->dc->debug.optimized_watermark) {
plane_res         328 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 		input->src.dcc = pipe->plane_res.dpp->ctx->dc->res_pool->hubbub->funcs->
plane_res         336 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	input->src.viewport_width      = pipe->plane_res.scl_data.viewport.width;
plane_res         337 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	input->src.viewport_height     = pipe->plane_res.scl_data.viewport.height;
plane_res         338 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	input->src.data_pitch          = pipe->plane_res.scl_data.viewport.width;
plane_res         339 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	input->src.data_pitch_c        = pipe->plane_res.scl_data.viewport.width;
plane_res         387 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	input->scale_taps.htaps                = pipe->plane_res.scl_data.taps.h_taps;
plane_res         388 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	input->scale_ratio_depth.hscl_ratio    = pipe->plane_res.scl_data.ratios.horz.value/4294967296.0;
plane_res         389 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	input->scale_ratio_depth.vscl_ratio    = pipe->plane_res.scl_data.ratios.vert.value/4294967296.0;
plane_res         390 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	input->scale_ratio_depth.vinit =  pipe->plane_res.scl_data.inits.v.value/4294967296.0;
plane_res         393 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	input->scale_taps.vtaps = pipe->plane_res.scl_data.taps.v_taps;
plane_res         394 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	input->scale_taps.vtaps_c = pipe->plane_res.scl_data.taps.v_taps_c;
plane_res         395 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	input->scale_taps.htaps_c              = pipe->plane_res.scl_data.taps.h_taps_c;
plane_res         396 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	input->scale_ratio_depth.hscl_ratio_c  = pipe->plane_res.scl_data.ratios.horz_c.value/4294967296.0;
plane_res         397 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	input->scale_ratio_depth.vscl_ratio_c  = pipe->plane_res.scl_data.ratios.vert_c.value/4294967296.0;
plane_res         398 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	input->scale_ratio_depth.vinit_c       = pipe->plane_res.scl_data.inits.v_c.value/4294967296.0;
plane_res         401 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	switch (pipe->plane_res.scl_data.lb_params.depth) {
plane_res         414 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	input->dest.recout_width   = pipe->plane_res.scl_data.recout.width;
plane_res         415 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	input->dest.recout_height  = pipe->plane_res.scl_data.recout.height;
plane_res         417 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	input->dest.full_recout_width   = pipe->plane_res.scl_data.recout.width;
plane_res         418 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	input->dest.full_recout_height  = pipe->plane_res.scl_data.recout.height;
plane_res         523 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx];
plane_res         524 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx];
plane_res         525 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	secondary_pipe->plane_res.ipp = pool->ipps[secondary_pipe->pipe_idx];
plane_res         526 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx];
plane_res         527 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx];
plane_res         528 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst;
plane_res         914 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			v->viewport_height[input_idx] =  pipe->plane_res.scl_data.viewport.height;
plane_res         915 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			v->viewport_width[input_idx] = pipe->plane_res.scl_data.viewport.width;
plane_res         916 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			v->scaler_rec_out_width[input_idx] = pipe->plane_res.scl_data.recout.width;
plane_res         917 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			v->scaler_recout_height[input_idx] = pipe->plane_res.scl_data.recout.height;
plane_res         920 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 					int viewport_end = pipe->plane_res.scl_data.viewport.width
plane_res         921 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 							+ pipe->plane_res.scl_data.viewport.x;
plane_res         922 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 					int viewport_b_end = pipe->bottom_pipe->plane_res.scl_data.viewport.width
plane_res         923 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 							+ pipe->bottom_pipe->plane_res.scl_data.viewport.x;
plane_res         927 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 							- pipe->bottom_pipe->plane_res.scl_data.viewport.x;
plane_res         930 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 									- pipe->plane_res.scl_data.viewport.x;
plane_res         932 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 					int viewport_end = pipe->plane_res.scl_data.viewport.height
plane_res         933 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 						+ pipe->plane_res.scl_data.viewport.y;
plane_res         934 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 					int viewport_b_end = pipe->bottom_pipe->plane_res.scl_data.viewport.height
plane_res         935 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 						+ pipe->bottom_pipe->plane_res.scl_data.viewport.y;
plane_res         939 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 							- pipe->bottom_pipe->plane_res.scl_data.viewport.y;
plane_res         942 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 									- pipe->plane_res.scl_data.viewport.y;
plane_res         944 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 				v->scaler_rec_out_width[input_idx] = pipe->plane_res.scl_data.recout.width
plane_res         945 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 						+ pipe->bottom_pipe->plane_res.scl_data.recout.width;
plane_res         949 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 				ASSERT(pipe->plane_res.scl_data.ratios.horz.value != dc_fixpt_one.value
plane_res         951 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 				ASSERT(pipe->plane_res.scl_data.ratios.vert.value != dc_fixpt_one.value
plane_res         954 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 				ASSERT(pipe->plane_res.scl_data.ratios.horz.value != dc_fixpt_one.value
plane_res         956 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 				ASSERT(pipe->plane_res.scl_data.ratios.vert.value != dc_fixpt_one.value
plane_res         983 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			v->lb_bit_per_pixel[input_idx] = tl_lb_bpp_to_int(pipe->plane_res.scl_data.lb_params.depth);
plane_res         984 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			v->override_hta_ps[input_idx] = pipe->plane_res.scl_data.taps.h_taps;
plane_res         985 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			v->override_vta_ps[input_idx] = pipe->plane_res.scl_data.taps.v_taps;
plane_res         986 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			v->override_hta_pschroma[input_idx] = pipe->plane_res.scl_data.taps.h_taps_c;
plane_res         987 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			v->override_vta_pschroma[input_idx] = pipe->plane_res.scl_data.taps.v_taps_c;
plane_res        1249 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 					memset(&hsplit_pipe->plane_res, 0, sizeof(hsplit_pipe->plane_res));
plane_res         107 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c 		pipe_ctx->plane_res.dpp->funcs->dpp_dppclk_control(
plane_res         108 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c 				pipe_ctx->plane_res.dpp,
plane_res         113 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 		dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;
plane_res         114 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 		dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
plane_res         287 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 				dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;
plane_res         288 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 				dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
plane_res         304 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 				dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;
plane_res         305 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 				dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
plane_res         443 drivers/gpu/drm/amd/display/dc/core/dc.c 	if (pipes->plane_res.xfm &&
plane_res         444 drivers/gpu/drm/amd/display/dc/core/dc.c 	    pipes->plane_res.xfm->funcs->transform_set_pixel_storage_depth) {
plane_res         445 drivers/gpu/drm/amd/display/dc/core/dc.c 		pipes->plane_res.xfm->funcs->transform_set_pixel_storage_depth(
plane_res         446 drivers/gpu/drm/amd/display/dc/core/dc.c 			pipes->plane_res.xfm,
plane_res         447 drivers/gpu/drm/amd/display/dc/core/dc.c 			pipes->plane_res.scl_data.lb_params.depth,
plane_res         551 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
plane_res         666 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	pipe_ctx->plane_res.scl_data.recout.x = stream->dst.x;
plane_res         668 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		pipe_ctx->plane_res.scl_data.recout.x += (surf_clip.x
plane_res         672 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	pipe_ctx->plane_res.scl_data.recout.width = surf_clip.width *
plane_res         674 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	if (pipe_ctx->plane_res.scl_data.recout.width + pipe_ctx->plane_res.scl_data.recout.x >
plane_res         676 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		pipe_ctx->plane_res.scl_data.recout.width =
plane_res         678 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 						- pipe_ctx->plane_res.scl_data.recout.x;
plane_res         680 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	pipe_ctx->plane_res.scl_data.recout.y = stream->dst.y;
plane_res         682 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		pipe_ctx->plane_res.scl_data.recout.y += (surf_clip.y
plane_res         686 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	pipe_ctx->plane_res.scl_data.recout.height = surf_clip.height *
plane_res         688 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	if (pipe_ctx->plane_res.scl_data.recout.height + pipe_ctx->plane_res.scl_data.recout.y >
plane_res         690 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		pipe_ctx->plane_res.scl_data.recout.height =
plane_res         692 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 						- pipe_ctx->plane_res.scl_data.recout.y;
plane_res         696 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		pipe_ctx->plane_res.scl_data.recout.y +=
plane_res         697 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 				pipe_ctx->plane_res.scl_data.recout.height / 2;
plane_res         699 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		pipe_ctx->plane_res.scl_data.recout.height =
plane_res         700 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 				(pipe_ctx->plane_res.scl_data.recout.height + 1) / 2;
plane_res         702 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		pipe_ctx->plane_res.scl_data.recout.height /= 2;
plane_res         704 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		pipe_ctx->plane_res.scl_data.recout.x +=
plane_res         705 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 				pipe_ctx->plane_res.scl_data.recout.width / 2;
plane_res         707 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		pipe_ctx->plane_res.scl_data.recout.width =
plane_res         708 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 				(pipe_ctx->plane_res.scl_data.recout.width + 1) / 2;
plane_res         710 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		pipe_ctx->plane_res.scl_data.recout.width /= 2;
plane_res         728 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_from_fraction(
plane_res         731 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_from_fraction(
plane_res         736 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		pipe_ctx->plane_res.scl_data.ratios.horz.value *= 2;
plane_res         738 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		pipe_ctx->plane_res.scl_data.ratios.vert.value *= 2;
plane_res         740 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	pipe_ctx->plane_res.scl_data.ratios.vert.value = div64_s64(
plane_res         741 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		pipe_ctx->plane_res.scl_data.ratios.vert.value * in_h, out_h);
plane_res         742 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	pipe_ctx->plane_res.scl_data.ratios.horz.value = div64_s64(
plane_res         743 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		pipe_ctx->plane_res.scl_data.ratios.horz.value * in_w, out_w);
plane_res         745 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	pipe_ctx->plane_res.scl_data.ratios.horz_c = pipe_ctx->plane_res.scl_data.ratios.horz;
plane_res         746 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	pipe_ctx->plane_res.scl_data.ratios.vert_c = pipe_ctx->plane_res.scl_data.ratios.vert;
plane_res         748 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	if (pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP8
plane_res         749 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 			|| pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP10) {
plane_res         750 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		pipe_ctx->plane_res.scl_data.ratios.horz_c.value /= 2;
plane_res         751 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		pipe_ctx->plane_res.scl_data.ratios.vert_c.value /= 2;
plane_res         753 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_truncate(
plane_res         754 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 			pipe_ctx->plane_res.scl_data.ratios.horz, 19);
plane_res         755 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_truncate(
plane_res         756 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 			pipe_ctx->plane_res.scl_data.ratios.vert, 19);
plane_res         757 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	pipe_ctx->plane_res.scl_data.ratios.horz_c = dc_fixpt_truncate(
plane_res         758 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 			pipe_ctx->plane_res.scl_data.ratios.horz_c, 19);
plane_res         759 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	pipe_ctx->plane_res.scl_data.ratios.vert_c = dc_fixpt_truncate(
plane_res         760 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 			pipe_ctx->plane_res.scl_data.ratios.vert_c, 19);
plane_res         847 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
plane_res         972 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	pipe_ctx->plane_res.scl_data.format = convert_pixel_format_to_dalsurface(
plane_res         979 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	if (pipe_ctx->plane_res.scl_data.viewport.height < 16 || pipe_ctx->plane_res.scl_data.viewport.width < 16)
plane_res         988 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
plane_res         990 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	pipe_ctx->plane_res.scl_data.recout.x += timing->h_border_left;
plane_res         991 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	pipe_ctx->plane_res.scl_data.recout.y += timing->v_border_top;
plane_res         993 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	pipe_ctx->plane_res.scl_data.h_active = timing->h_addressable + timing->h_border_left + timing->h_border_right;
plane_res         994 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	pipe_ctx->plane_res.scl_data.v_active = timing->v_addressable + timing->v_border_top + timing->v_border_bottom;
plane_res         997 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	if (pipe_ctx->plane_res.xfm != NULL)
plane_res         998 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(
plane_res         999 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 				pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
plane_res        1001 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	if (pipe_ctx->plane_res.dpp != NULL)
plane_res        1002 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
plane_res        1003 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 				pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
plane_res        1007 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	    are_rect_integer_multiples(pipe_ctx->plane_res.scl_data.viewport,
plane_res        1008 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 				       pipe_ctx->plane_res.scl_data.recout)) {
plane_res        1009 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		pipe_ctx->plane_res.scl_data.taps.v_taps = 1;
plane_res        1010 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		pipe_ctx->plane_res.scl_data.taps.h_taps = 1;
plane_res        1015 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_24BPP;
plane_res        1017 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		if (pipe_ctx->plane_res.xfm != NULL)
plane_res        1018 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 			res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(
plane_res        1019 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 					pipe_ctx->plane_res.xfm,
plane_res        1020 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 					&pipe_ctx->plane_res.scl_data,
plane_res        1023 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		if (pipe_ctx->plane_res.dpp != NULL)
plane_res        1024 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 			res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
plane_res        1025 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 					pipe_ctx->plane_res.dpp,
plane_res        1026 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 					&pipe_ctx->plane_res.scl_data,
plane_res        1039 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 				pipe_ctx->plane_res.scl_data.viewport.height,
plane_res        1040 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 				pipe_ctx->plane_res.scl_data.viewport.width,
plane_res        1041 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 				pipe_ctx->plane_res.scl_data.viewport.x,
plane_res        1042 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 				pipe_ctx->plane_res.scl_data.viewport.y,
plane_res        1215 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 			split_pipe->plane_res.hubp = pool->hubps[i];
plane_res        1216 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 			split_pipe->plane_res.ipp = pool->ipps[i];
plane_res        1217 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 			split_pipe->plane_res.dpp = pool->dpps[i];
plane_res        1219 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 			split_pipe->plane_res.mpcc_inst = pool->dpps[i]->inst;
plane_res        1617 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 			pipe_ctx->plane_res.mi = pool->mis[i];
plane_res        1618 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 			pipe_ctx->plane_res.hubp = pool->hubps[i];
plane_res        1619 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 			pipe_ctx->plane_res.ipp = pool->ipps[i];
plane_res        1620 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 			pipe_ctx->plane_res.xfm = pool->transforms[i];
plane_res        1621 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 			pipe_ctx->plane_res.dpp = pool->dpps[i];
plane_res        1624 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 				pipe_ctx->plane_res.mpcc_inst = pool->dpps[i]->inst;
plane_res        1887 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		pipe_ctx->plane_res.mi = pool->mis[tg_inst];
plane_res        1888 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		pipe_ctx->plane_res.hubp = pool->hubps[tg_inst];
plane_res        1889 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		pipe_ctx->plane_res.ipp = pool->ipps[tg_inst];
plane_res        1890 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		pipe_ctx->plane_res.xfm = pool->transforms[tg_inst];
plane_res        1891 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		pipe_ctx->plane_res.dpp = pool->dpps[tg_inst];
plane_res        1895 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 			pipe_ctx->plane_res.mpcc_inst = pool->dpps[tg_inst]->inst;
plane_res         348 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 				(!pipe_ctx->plane_res.mi  && !pipe_ctx->plane_res.hubp) ||
plane_res         350 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 				(!pipe_ctx->plane_res.xfm && !pipe_ctx->plane_res.dpp) ||
plane_res         351 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 				(!pipe_ctx->plane_res.ipp && !pipe_ctx->plane_res.dpp))
plane_res         618 drivers/gpu/drm/amd/display/dc/core/dc_stream.c 	hubp = pipe_ctx->plane_res.hubp;
plane_res         274 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
plane_res         602 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	struct transform *xfm = pipe_ctx->plane_res.xfm;
plane_res        1198 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	switch (pipe_ctx->plane_res.scl_data.format) {
plane_res        1235 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	if (pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth == NULL)
plane_res        1246 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth(
plane_res        1247 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		pipe_ctx->plane_res.xfm,
plane_res        1248 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		pipe_ctx->plane_res.scl_data.lb_params.depth,
plane_res        1265 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm,
plane_res        1266 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		&pipe_ctx->plane_res.scl_data);
plane_res        1419 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
plane_res        1662 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		pipe_ctx->plane_res.mi->funcs->mem_input_program_display_marks(
plane_res        1663 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 			pipe_ctx->plane_res.mi,
plane_res        1671 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 			pipe_ctx->plane_res.mi->funcs->mem_input_program_chroma_display_marks(
plane_res        1672 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 				pipe_ctx->plane_res.mi,
plane_res        1695 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		if (res_ctx->pipe_ctx[i].stream == NULL || res_ctx->pipe_ctx[i].plane_res.mi == NULL)
plane_res        1698 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_display_marks(
plane_res        1699 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 				res_ctx->pipe_ctx[i].plane_res.mi,
plane_res        1707 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 			res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_chroma_display_marks(
plane_res        1708 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 				res_ctx->pipe_ctx[i].plane_res.mi,
plane_res        1933 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 			pipe_ctx_old->plane_res.mi->funcs->free_mem_input(
plane_res        1934 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 					pipe_ctx_old->plane_res.mi, dc->current_state->stream_count);
plane_res        2121 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	default_adjust.surface_pixel_format = pipe_ctx->plane_res.scl_data.format;
plane_res        2128 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	default_adjust.lb_color_depth = pipe_ctx->plane_res.scl_data.lb_params.depth;
plane_res        2130 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	pipe_ctx->plane_res.xfm->funcs->opp_set_csc_default(
plane_res        2131 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 					pipe_ctx->plane_res.xfm, &default_adjust);
plane_res        2198 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);
plane_res        2208 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	pipe_ctx->plane_res.mi->funcs->mem_input_program_surface_flip_and_addr(
plane_res        2209 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 			pipe_ctx->plane_res.mi,
plane_res        2224 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 			pipe_ctx->plane_res.mi->funcs->mem_input_is_flip_pending(
plane_res        2225 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 					pipe_ctx->plane_res.mi);
plane_res        2228 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		pipe_ctx->plane_res.mi->current_address = pipe_ctx->plane_res.mi->request_address;
plane_res        2230 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	plane_state->status.current_address = pipe_ctx->plane_res.mi->current_address;
plane_res        2231 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	if (pipe_ctx->plane_res.mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
plane_res        2466 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	struct mem_input *mi = pipe_ctx->plane_res.mi;
plane_res        2493 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment
plane_res        2494 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 				(pipe_ctx->plane_res.xfm, &tbl_entry);
plane_res        2505 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);
plane_res        2507 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
plane_res        2524 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 				pipe_ctx->plane_res.mi,
plane_res        2566 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 			pipe_ctx->plane_res.scl_data.viewport.width,
plane_res        2567 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 			pipe_ctx->plane_res.scl_data.viewport.height,
plane_res        2568 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 			pipe_ctx->plane_res.scl_data.viewport.x,
plane_res        2569 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 			pipe_ctx->plane_res.scl_data.viewport.y,
plane_res        2570 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 			pipe_ctx->plane_res.scl_data.recout.width,
plane_res        2571 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 			pipe_ctx->plane_res.scl_data.recout.height,
plane_res        2572 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 			pipe_ctx->plane_res.scl_data.recout.x,
plane_res        2573 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 			pipe_ctx->plane_res.scl_data.recout.y);
plane_res        2608 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		pipe_ctx->plane_res.mi->funcs->allocate_mem_input(
plane_res        2609 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 				pipe_ctx->plane_res.mi,
plane_res        2639 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	int fe_idx = pipe_ctx->plane_res.mi ?
plane_res        2640 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		pipe_ctx->plane_res.mi->inst : pipe_ctx->pipe_idx;
plane_res        2678 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment(
plane_res        2679 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 				pipe_ctx->plane_res.xfm, &tbl_entry);
plane_res        2686 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
plane_res        2687 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	struct mem_input *mi = pipe_ctx->plane_res.mi;
plane_res        2691 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		.viewport = pipe_ctx->plane_res.scl_data.viewport,
plane_res        2692 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		.h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz,
plane_res        2693 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		.v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert,
plane_res        2715 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	if (pipe_ctx->plane_res.ipp &&
plane_res        2716 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	    pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes)
plane_res        2717 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes(
plane_res        2718 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 				pipe_ctx->plane_res.ipp, attributes);
plane_res        2720 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	if (pipe_ctx->plane_res.mi &&
plane_res        2721 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	    pipe_ctx->plane_res.mi->funcs->set_cursor_attributes)
plane_res        2722 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		pipe_ctx->plane_res.mi->funcs->set_cursor_attributes(
plane_res        2723 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 				pipe_ctx->plane_res.mi, attributes);
plane_res        2725 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	if (pipe_ctx->plane_res.xfm &&
plane_res        2726 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	    pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes)
plane_res        2727 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes(
plane_res        2728 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 				pipe_ctx->plane_res.xfm, attributes);
plane_res        1062 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 	pipe_ctx->plane_res.mi = pool->mis[underlay_idx];
plane_res        1064 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 	pipe_ctx->plane_res.xfm = pool->transforms[underlay_idx];
plane_res        1098 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 		pipe_ctx->plane_res.mi->funcs->allocate_mem_input(pipe_ctx->plane_res.mi,
plane_res         426 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	struct hubp *hubp = pipe_ctx->plane_res.hubp;
plane_res         888 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			hubp = pipe_ctx->plane_res.hubp;
plane_res         913 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			hubp = pipe_ctx->plane_res.hubp;
plane_res         926 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			hubp = pipe_ctx->plane_res.hubp;
plane_res         936 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			hubp = pipe_ctx->plane_res.hubp;
plane_res         948 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			hubp = pipe_ctx->plane_res.hubp;
plane_res         979 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	struct hubp *hubp = pipe_ctx->plane_res.hubp;
plane_res         980 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	int dpp_id = pipe_ctx->plane_res.dpp->inst;
plane_res         995 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		opp->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
plane_res        1031 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	struct hubp *hubp = pipe_ctx->plane_res.hubp;
plane_res        1032 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	struct dpp *dpp = pipe_ctx->plane_res.dpp;
plane_res        1050 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			pipe_ctx->plane_res.dpp,
plane_res        1051 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			pipe_ctx->plane_res.hubp);
plane_res        1055 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res));
plane_res        1065 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated)
plane_res        1149 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		pipe_ctx->plane_res.hubp = hubp;
plane_res        1150 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		pipe_ctx->plane_res.dpp = dpp;
plane_res        1151 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		pipe_ctx->plane_res.mpcc_inst = dpp->inst;
plane_res        1158 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
plane_res        1169 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		pipe_ctx->plane_res.hubp = NULL;
plane_res        1375 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr(
plane_res        1376 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			pipe_ctx->plane_res.hubp,
plane_res        1392 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
plane_res        1471 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	struct dpp *dpp = pipe_ctx->plane_res.dpp;
plane_res        1839 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		pipe_ctx->plane_res.hubp->inst);
plane_res        1842 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true);
plane_res        1887 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		dcn10_program_pte_vm(hws, pipe_ctx->plane_res.hubp);
plane_res        1909 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	pipe_ctx->plane_res.dpp->funcs->dpp_set_gamut_remap(pipe_ctx->plane_res.dpp, &adjust);
plane_res        1936 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment(pipe_ctx->plane_res.dpp, matrix);
plane_res        1949 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment != NULL) {
plane_res        1965 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 				pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment(pipe_ctx->plane_res.dpp, matrix);
plane_res        1969 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default != NULL)
plane_res        1970 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default(pipe_ctx->plane_res.dpp, colorspace);
plane_res        2031 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	switch (pipe_ctx->plane_res.scl_data.format) {
plane_res        2073 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	switch (top_pipe_ctx->plane_res.scl_data.format) {
plane_res        2185 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	struct hubp *hubp = pipe_ctx->plane_res.hubp;
plane_res        2272 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	pipe_ctx->plane_res.scl_data.lb_params.alpha_en = per_pixel_alpha;
plane_res        2273 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
plane_res        2275 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler(
plane_res        2276 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data);
plane_res        2284 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	struct hubp *hubp = pipe_ctx->plane_res.hubp;
plane_res        2285 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	struct dpp *dpp = pipe_ctx->plane_res.dpp;
plane_res        2307 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 					pipe_ctx->plane_res.bw.dppclk_khz,
plane_res        2334 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	size.surface_size = pipe_ctx->plane_res.scl_data.viewport;
plane_res        2358 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			&pipe_ctx->plane_res.scl_data.viewport,
plane_res        2359 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			&pipe_ctx->plane_res.scl_data.viewport_c);
plane_res        2466 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	pipe_ctx->plane_res.dpp->funcs->dpp_set_hdr_multiplier(
plane_res        2467 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			pipe_ctx->plane_res.dpp, hw_mult);
plane_res        2607 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			    old_pipe_ctx->plane_res.hubp &&
plane_res        2608 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			    old_pipe_ctx->plane_res.hubp->opp_id != OPP_ID_INVALID)
plane_res        2641 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			pipe_ctx->plane_res.hubp->funcs->hubp_setup_interdependent(
plane_res        2642 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 				pipe_ctx->plane_res.hubp,
plane_res        2931 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	flip_pending = pipe_ctx->plane_res.hubp->funcs->hubp_is_flip_pending(
plane_res        2932 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 					pipe_ctx->plane_res.hubp);
plane_res        2957 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	struct hubp *hubp = pipe_ctx->plane_res.hubp;
plane_res        2958 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	struct dpp *dpp = pipe_ctx->plane_res.dpp;
plane_res        2962 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		.viewport = pipe_ctx->plane_res.scl_data.viewport,
plane_res        2963 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		.h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz,
plane_res        2964 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		.v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert,
plane_res        2985 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		pos_cpy.x = pipe_ctx->plane_res.scl_data.viewport.width -
plane_res        2986 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 				(pos_cpy.y - pipe_ctx->plane_res.scl_data.viewport.x) + pipe_ctx->plane_res.scl_data.viewport.x;
plane_res        2992 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		if (pos_cpy.x >  pipe_ctx->plane_res.scl_data.viewport.height) {
plane_res        2993 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			pos_cpy.x = pos_cpy.x - pipe_ctx->plane_res.scl_data.viewport.height;
plane_res        2994 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			pos_cpy.y = pipe_ctx->plane_res.scl_data.viewport.height - pos_cpy.x;
plane_res        2996 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			pos_cpy.y = 2 * pipe_ctx->plane_res.scl_data.viewport.height - pos_cpy.x;
plane_res        3002 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		if (pos_cpy.x >= pipe_ctx->plane_res.scl_data.viewport.width + pipe_ctx->plane_res.scl_data.viewport.x) {
plane_res        3003 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			pos_cpy.x = 2 * pipe_ctx->plane_res.scl_data.viewport.width
plane_res        3004 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 					- pos_cpy.x + 2 * pipe_ctx->plane_res.scl_data.viewport.x;
plane_res        3007 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			pos_cpy.x = 2 * pipe_ctx->plane_res.scl_data.viewport.x - pos_cpy.x;
plane_res        3008 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			if (temp_x >= pipe_ctx->plane_res.scl_data.viewport.x + (int)hubp->curs_attr.width
plane_res        3010 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 				pos_cpy.x = temp_x + pipe_ctx->plane_res.scl_data.viewport.width;
plane_res        3013 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		pos_cpy.y = pipe_ctx->plane_res.scl_data.viewport.height - pos_cpy.y;
plane_res        3024 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	pipe_ctx->plane_res.hubp->funcs->set_cursor_attributes(
plane_res        3025 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			pipe_ctx->plane_res.hubp, attributes);
plane_res        3026 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	pipe_ctx->plane_res.dpp->funcs->set_cursor_attributes(
plane_res        3027 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		pipe_ctx->plane_res.dpp, attributes);
plane_res        3038 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (!pipe_ctx->plane_res.dpp->funcs->set_optional_cursor_attributes)
plane_res        3053 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	pipe_ctx->plane_res.dpp->funcs->set_optional_cursor_attributes(
plane_res        3054 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			pipe_ctx->plane_res.dpp, &opt_attr);
plane_res        1110 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];
plane_res        1111 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx];
plane_res        1112 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx];
plane_res        1113 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst;
plane_res         186 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	if (pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->funcs) {
plane_res         187 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		pipe_ctx->plane_res.hubp->funcs->hubp_enable_tripleBuffer(
plane_res         188 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 			pipe_ctx->plane_res.hubp,
plane_res         478 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	struct hubp *hubp = pipe_ctx->plane_res.hubp;
plane_res         479 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	struct dpp *dpp = pipe_ctx->plane_res.dpp;
plane_res         498 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 			pipe_ctx->plane_res.dpp,
plane_res         499 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 			pipe_ctx->plane_res.hubp);
plane_res         503 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res));
plane_res         514 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated)
plane_res         631 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	int mpcc_id = pipe_ctx->plane_res.hubp->inst;
plane_res         654 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	int mpcc_id = pipe_ctx->plane_res.hubp->inst;
plane_res         693 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
plane_res         715 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
plane_res         752 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
plane_res         916 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		dcn20_dpp_pg_control(hws, pipe_ctx->plane_res.dpp->inst, true);
plane_res         917 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		dcn20_hubp_pg_control(hws, pipe_ctx->plane_res.hubp->inst, true);
plane_res         921 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 				"Un-gated front end for pipe %d\n", pipe_ctx->plane_res.hubp->inst);
plane_res         936 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true);
plane_res         939 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	pipe_ctx->plane_res.hubp->funcs->hubp_init(pipe_ctx->plane_res.hubp);
plane_res         992 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		pipe_ctx->plane_res.hubp->funcs->hubp_set_vm_system_aperture_settings(pipe_ctx->plane_res.hubp, &apt);
plane_res        1110 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 			if (!pipe->plane_res.hubp->funcs->hubp_is_flip_pending(pipe->plane_res.hubp))
plane_res        1117 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 				if (!pipe->bottom_pipe->plane_res.hubp->funcs->hubp_is_flip_pending(pipe->bottom_pipe->plane_res.hubp))
plane_res        1205 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 			    old_pipe_ctx->plane_res.hubp &&
plane_res        1206 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 			    old_pipe_ctx->plane_res.hubp->opp_id != OPP_ID_INVALID)
plane_res        1239 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 			pipe_ctx->plane_res.hubp->funcs->hubp_setup_interdependent(
plane_res        1240 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 				pipe_ctx->plane_res.hubp,
plane_res        1264 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 				top_pipe_to_program->plane_res.hubp->funcs->hubp_is_flip_pending(top_pipe_to_program->plane_res.hubp)) {
plane_res        1344 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		pipe_ctx->plane_res.hubp->funcs->hubp_setup(
plane_res        1345 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 				pipe_ctx->plane_res.hubp,
plane_res        1421 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	struct hubp *hubp = pipe_ctx->plane_res.hubp;
plane_res        1465 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	struct hubp *hubp = pipe_ctx->plane_res.hubp;
plane_res        1566 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	vm_helper_mark_vmid_used(dc->vm_helper, plane_state->address.vmid, pipe_ctx->plane_res.hubp->inst);
plane_res        1568 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr(
plane_res        1569 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 			pipe_ctx->plane_res.hubp,
plane_res        1726 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	struct hubp *hubp = pipe_ctx->plane_res.hubp;
plane_res        1915 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	if (pipe_ctx && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl)
plane_res        1916 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl(
plane_res        1917 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 				pipe_ctx->plane_res.hubp, flip_immediate);
plane_res        1970 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	struct hubp               *hubp       = pipe_ctx->plane_res.hubp;
plane_res        2064 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		pipe_ctx->plane_res.hubp = hubp;
plane_res        2065 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		pipe_ctx->plane_res.dpp = dpp;
plane_res        2066 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		pipe_ctx->plane_res.mpcc_inst = dpp->inst;
plane_res        2076 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
plane_res        2099 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		pipe_ctx->plane_res.hubp = NULL;
plane_res        1733 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	next_odm_pipe->plane_res.mi = pool->mis[next_odm_pipe->pipe_idx];
plane_res        1734 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	next_odm_pipe->plane_res.hubp = pool->hubps[next_odm_pipe->pipe_idx];
plane_res        1735 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	next_odm_pipe->plane_res.ipp = pool->ipps[next_odm_pipe->pipe_idx];
plane_res        1736 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	next_odm_pipe->plane_res.xfm = pool->transforms[next_odm_pipe->pipe_idx];
plane_res        1737 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	next_odm_pipe->plane_res.dpp = pool->dpps[next_odm_pipe->pipe_idx];
plane_res        1738 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	next_odm_pipe->plane_res.mpcc_inst = pool->dpps[next_odm_pipe->pipe_idx]->inst;
plane_res        1752 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		struct scaler_data *sd = &prev_odm_pipe->plane_res.scl_data;
plane_res        1769 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		sd = &next_odm_pipe->plane_res.scl_data;
plane_res        1813 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx];
plane_res        1814 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx];
plane_res        1815 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	secondary_pipe->plane_res.ipp = pool->ipps[secondary_pipe->pipe_idx];
plane_res        1816 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx];
plane_res        1817 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx];
plane_res        1818 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst;
plane_res        2072 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			struct scaler_data *scl = &res_ctx->pipe_ctx[i].plane_res.scl_data;
plane_res        2103 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 						res_ctx->pipe_ctx[i].bottom_pipe->plane_res.scl_data.recout.width;
plane_res        2105 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 						res_ctx->pipe_ctx[i].bottom_pipe->plane_res.scl_data.recout.height;
plane_res        2108 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 						res_ctx->pipe_ctx[i].top_pipe->plane_res.scl_data.recout.width;
plane_res        2110 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 						res_ctx->pipe_ctx[i].top_pipe->plane_res.scl_data.recout.height;
plane_res        2411 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			memset(&odm_pipe->plane_res, 0, sizeof(odm_pipe->plane_res));
plane_res        2436 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		memset(&hsplit_pipe->plane_res, 0, sizeof(hsplit_pipe->plane_res));
plane_res        2803 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz =
plane_res        2953 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];
plane_res        2954 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx];
plane_res        2955 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx];
plane_res        2956 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst;
plane_res         292 drivers/gpu/drm/amd/display/dc/inc/core_types.h 	struct plane_resource plane_res;