plane1_base_address  549 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 			DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address);
plane1_base_address  856 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 			DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs->plane1_base_address);
plane1_base_address  174 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 				rq_regs->crq_expansion_mode, rq_regs->plane1_base_address, rq_regs->rq_regs_l.chunk_size,
plane1_base_address  213 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 				rq_regs->crq_expansion_mode, rq_regs->plane1_base_address, rq_regs->rq_regs_l.chunk_size,
plane1_base_address  197 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 			DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address);
plane1_base_address 1054 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 			DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs->plane1_base_address);
plane1_base_address  123 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c 			DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address);
plane1_base_address  231 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 	rq_regs->plane1_base_address = detile_buf_plane1_addr;
plane1_base_address  231 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 	rq_regs->plane1_base_address = detile_buf_plane1_addr;
plane1_base_address  213 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 	rq_regs->plane1_base_address = detile_buf_plane1_addr;
plane1_base_address  501 drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h 	unsigned int plane1_base_address;
plane1_base_address  190 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c 	dml_print("DML_RQ_DLG_CALC:    plane1_base_address = 0x%0x\n", rq_regs.plane1_base_address);
plane1_base_address  269 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 	rq_regs->plane1_base_address = detile_buf_plane1_addr;