pl2                85 arch/x86/kernel/head32.c 	pmd_t pl2, *pl2p = (pmd_t *)__pa(initial_pg_pmd);
pl2                86 arch/x86/kernel/head32.c #define SET_PL2(pl2, val)    { (pl2).pmd = (val); }
pl2                88 arch/x86/kernel/head32.c 	pgd_t pl2, *pl2p = (pgd_t *)__pa(initial_page_table);
pl2                89 arch/x86/kernel/head32.c #define SET_PL2(pl2, val)   { (pl2).pgd = (val); }
pl2                97 arch/x86/kernel/head32.c 		SET_PL2(pl2, (unsigned long)ptep | PDE_IDENT_ATTR);
pl2                98 arch/x86/kernel/head32.c 		*pl2p = pl2;
pl2               101 arch/x86/kernel/head32.c 		*(pl2p +  ((PAGE_OFFSET >> PGDIR_SHIFT))) = pl2;
pl2              4186 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 							   const struct smu7_performance_level *pl2)
pl2              4188 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	return ((pl1->memory_clock == pl2->memory_clock) &&
pl2              4189 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		  (pl1->engine_clock == pl2->engine_clock) &&
pl2              4190 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		  (pl1->pcie_gen == pl2->pcie_gen) &&
pl2              4191 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		  (pl1->pcie_lane == pl2->pcie_lane));
pl2              4636 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 				const struct vega10_performance_level *pl2)
pl2              4638 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	return ((pl1->soc_clock == pl2->soc_clock) &&
pl2              4639 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			(pl1->gfx_clock == pl2->gfx_clock) &&
pl2              4640 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			(pl1->mem_clock == pl2->mem_clock));