pl172              63 drivers/memory/pl172.c 	struct pl172_data *pl172 = amba_get_drvdata(adev);
pl172              68 drivers/memory/pl172.c 		cycles = DIV_ROUND_UP(val * pl172->rate, NSEC_PER_MSEC) - start;
pl172              76 drivers/memory/pl172.c 		writel(cycles, pl172->base + reg_offset);
pl172              80 drivers/memory/pl172.c 				readl(pl172->base + reg_offset));
pl172              88 drivers/memory/pl172.c 	struct pl172_data *pl172 = amba_get_drvdata(adev);
pl172             128 drivers/memory/pl172.c 	writel(cfg, pl172->base + MPMC_STATIC_CFG(cs));
pl172             202 drivers/memory/pl172.c 	struct pl172_data *pl172;
pl172             218 drivers/memory/pl172.c 	pl172 = devm_kzalloc(dev, sizeof(*pl172), GFP_KERNEL);
pl172             219 drivers/memory/pl172.c 	if (!pl172)
pl172             222 drivers/memory/pl172.c 	pl172->clk = devm_clk_get(dev, "mpmcclk");
pl172             223 drivers/memory/pl172.c 	if (IS_ERR(pl172->clk)) {
pl172             225 drivers/memory/pl172.c 		return PTR_ERR(pl172->clk);
pl172             228 drivers/memory/pl172.c 	ret = clk_prepare_enable(pl172->clk);
pl172             234 drivers/memory/pl172.c 	pl172->rate = clk_get_rate(pl172->clk) / MSEC_PER_SEC;
pl172             235 drivers/memory/pl172.c 	if (!pl172->rate) {
pl172             247 drivers/memory/pl172.c 	pl172->base = devm_ioremap(dev, adev->res.start,
pl172             249 drivers/memory/pl172.c 	if (!pl172->base) {
pl172             255 drivers/memory/pl172.c 	amba_set_drvdata(adev, pl172);
pl172             275 drivers/memory/pl172.c 	clk_disable_unprepare(pl172->clk);
pl172             281 drivers/memory/pl172.c 	struct pl172_data *pl172 = amba_get_drvdata(adev);
pl172             283 drivers/memory/pl172.c 	clk_disable_unprepare(pl172->clk);