pko_mem_port_rate1  590 arch/mips/cavium-octeon/executive/cvmx-pko.c 	union cvmx_pko_mem_port_rate1 pko_mem_port_rate1;
pko_mem_port_rate1  599 arch/mips/cavium-octeon/executive/cvmx-pko.c 	pko_mem_port_rate1.u64 = 0;
pko_mem_port_rate1  600 arch/mips/cavium-octeon/executive/cvmx-pko.c 	pko_mem_port_rate1.s.pid = port;
pko_mem_port_rate1  601 arch/mips/cavium-octeon/executive/cvmx-pko.c 	pko_mem_port_rate1.s.rate_lim =
pko_mem_port_rate1  605 arch/mips/cavium-octeon/executive/cvmx-pko.c 	cvmx_write_csr(CVMX_PKO_MEM_PORT_RATE1, pko_mem_port_rate1.u64);
pko_mem_port_rate1  623 arch/mips/cavium-octeon/executive/cvmx-pko.c 	union cvmx_pko_mem_port_rate1 pko_mem_port_rate1;
pko_mem_port_rate1  639 arch/mips/cavium-octeon/executive/cvmx-pko.c 	pko_mem_port_rate1.u64 = 0;
pko_mem_port_rate1  640 arch/mips/cavium-octeon/executive/cvmx-pko.c 	pko_mem_port_rate1.s.pid = port;
pko_mem_port_rate1  641 arch/mips/cavium-octeon/executive/cvmx-pko.c 	pko_mem_port_rate1.s.rate_lim = tokens_per_bit * burst / 256;
pko_mem_port_rate1  644 arch/mips/cavium-octeon/executive/cvmx-pko.c 	cvmx_write_csr(CVMX_PKO_MEM_PORT_RATE1, pko_mem_port_rate1.u64);