pko_mem_port_rate0  589 arch/mips/cavium-octeon/executive/cvmx-pko.c 	union cvmx_pko_mem_port_rate0 pko_mem_port_rate0;
pko_mem_port_rate0  592 arch/mips/cavium-octeon/executive/cvmx-pko.c 	pko_mem_port_rate0.u64 = 0;
pko_mem_port_rate0  593 arch/mips/cavium-octeon/executive/cvmx-pko.c 	pko_mem_port_rate0.s.pid = port;
pko_mem_port_rate0  594 arch/mips/cavium-octeon/executive/cvmx-pko.c 	pko_mem_port_rate0.s.rate_pkt =
pko_mem_port_rate0  597 arch/mips/cavium-octeon/executive/cvmx-pko.c 	pko_mem_port_rate0.s.rate_word = 0;
pko_mem_port_rate0  602 arch/mips/cavium-octeon/executive/cvmx-pko.c 	    ((uint64_t) pko_mem_port_rate0.s.rate_pkt * burst) >> 8;
pko_mem_port_rate0  604 arch/mips/cavium-octeon/executive/cvmx-pko.c 	cvmx_write_csr(CVMX_PKO_MEM_PORT_RATE0, pko_mem_port_rate0.u64);
pko_mem_port_rate0  622 arch/mips/cavium-octeon/executive/cvmx-pko.c 	union cvmx_pko_mem_port_rate0 pko_mem_port_rate0;
pko_mem_port_rate0  627 arch/mips/cavium-octeon/executive/cvmx-pko.c 	pko_mem_port_rate0.u64 = 0;
pko_mem_port_rate0  628 arch/mips/cavium-octeon/executive/cvmx-pko.c 	pko_mem_port_rate0.s.pid = port;
pko_mem_port_rate0  635 arch/mips/cavium-octeon/executive/cvmx-pko.c 	pko_mem_port_rate0.s.rate_pkt = (12 + 8 + 4) * 8 * tokens_per_bit / 256;
pko_mem_port_rate0  637 arch/mips/cavium-octeon/executive/cvmx-pko.c 	pko_mem_port_rate0.s.rate_word = 64 * tokens_per_bit;
pko_mem_port_rate0  643 arch/mips/cavium-octeon/executive/cvmx-pko.c 	cvmx_write_csr(CVMX_PKO_MEM_PORT_RATE0, pko_mem_port_rate0.u64);