pixel_rep         301 drivers/gpu/drm/vc4/vc4_crtc.c 	u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
pixel_rep         313 drivers/gpu/drm/vc4/vc4_crtc.c 				  mode->hsync_end) * pixel_rep,
pixel_rep         316 drivers/gpu/drm/vc4/vc4_crtc.c 				  mode->hsync_start) * pixel_rep,
pixel_rep         320 drivers/gpu/drm/vc4/vc4_crtc.c 				  mode->hdisplay) * pixel_rep,
pixel_rep         322 drivers/gpu/drm/vc4/vc4_crtc.c 		   VC4_SET_FIELD(mode->hdisplay * pixel_rep, PV_HORZB_HACTIVE));
pixel_rep         357 drivers/gpu/drm/vc4/vc4_crtc.c 			   VC4_SET_FIELD(mode->htotal * pixel_rep / 2,
pixel_rep         366 drivers/gpu/drm/vc4/vc4_crtc.c 	CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep);
pixel_rep         372 drivers/gpu/drm/vc4/vc4_crtc.c 		   VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) |
pixel_rep         480 drivers/gpu/drm/vc4/vc4_hdmi.c 	u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
pixel_rep         548 drivers/gpu/drm/vc4/vc4_hdmi.c 		   VC4_SET_FIELD(mode->hdisplay * pixel_rep,
pixel_rep         553 drivers/gpu/drm/vc4/vc4_hdmi.c 				  mode->hsync_end) * pixel_rep,
pixel_rep         556 drivers/gpu/drm/vc4/vc4_hdmi.c 				  mode->hsync_start) * pixel_rep,
pixel_rep         559 drivers/gpu/drm/vc4/vc4_hdmi.c 				  mode->hdisplay) * pixel_rep,
pixel_rep          87 drivers/video/fbdev/aty/mach64_gx.c 		u8 pixel_rep;
pixel_rep         117 drivers/video/fbdev/aty/mach64_gx.c 	aty_st_514(0x0a, tab[i].pixel_rep, par);	/* Pixel Format */