pixclk             42 arch/arm/mach-rpc/include/mach/acornfb.h acornfb_vidc20_find_pll(u_int pixclk)
pixclk             53 arch/arm/mach-rpc/include/mach/acornfb.h 		v = (rr + pixclk / 2) / pixclk;
pixclk             60 arch/arm/mach-rpc/include/mach/acornfb.h 		d = pixclk - p;
pixclk            868 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c 	info->lcd_timing.pixel_clk = le16_to_cpu(lvds->lcd_timing.pixclk) * 10;
pixclk            430 drivers/gpu/drm/amd/include/atomfirmware.h   uint16_t  pixclk;
pixclk             15 drivers/gpu/drm/msm/disp/mdp4/mdp4_lvds_pll.c 	unsigned long pixclk;
pixclk             61 drivers/gpu/drm/msm/disp/mdp4/mdp4_lvds_pll.c 	const struct pll_rate *pll_rate = find_rate(lvds_pll->pixclk);
pixclk             64 drivers/gpu/drm/msm/disp/mdp4/mdp4_lvds_pll.c 	DBG("pixclk=%lu (%lu)", lvds_pll->pixclk, pll_rate->rate);
pixclk             98 drivers/gpu/drm/msm/disp/mdp4/mdp4_lvds_pll.c 	return lvds_pll->pixclk;
pixclk            112 drivers/gpu/drm/msm/disp/mdp4/mdp4_lvds_pll.c 	lvds_pll->pixclk = rate;
pixclk             18 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c 	unsigned long pixclk;
pixclk            373 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c 	return pll->pixclk;
pixclk            396 drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c 	pll->pixclk = rate;
pixclk            130 drivers/gpu/drm/zte/zx_vou.c 	struct clk *pixclk;
pixclk            446 drivers/gpu/drm/zte/zx_vou.c 	ret = clk_set_rate(zcrtc->pixclk, mode->clock * 1000);
pixclk            452 drivers/gpu/drm/zte/zx_vou.c 	ret = clk_prepare_enable(zcrtc->pixclk);
pixclk            464 drivers/gpu/drm/zte/zx_vou.c 	clk_disable_unprepare(zcrtc->pixclk);
pixclk            576 drivers/gpu/drm/zte/zx_vou.c 	zcrtc->pixclk = devm_clk_get(dev, (chn_type == VOU_CHN_MAIN) ?
pixclk            578 drivers/gpu/drm/zte/zx_vou.c 	if (IS_ERR(zcrtc->pixclk)) {
pixclk            579 drivers/gpu/drm/zte/zx_vou.c 		ret = PTR_ERR(zcrtc->pixclk);
pixclk            816 drivers/staging/media/soc_camera/soc_mt9v022.c 	u16 pixclk = 0;
pixclk            831 drivers/staging/media/soc_camera/soc_mt9v022.c 		pixclk |= 0x10;
pixclk            834 drivers/staging/media/soc_camera/soc_mt9v022.c 		pixclk |= 0x1;
pixclk            837 drivers/staging/media/soc_camera/soc_mt9v022.c 		pixclk |= 0x2;
pixclk            839 drivers/staging/media/soc_camera/soc_mt9v022.c 	ret = reg_write(client, mt9v022->reg->pixclk_fv_lv, pixclk);
pixclk            851 drivers/staging/media/soc_camera/soc_mt9v022.c 		pixclk, mt9v022->chip_control);
pixclk             48 drivers/video/fbdev/broadsheetfb.c 	u16 pixclk;
pixclk             63 drivers/video/fbdev/broadsheetfb.c 		.pixclk = 6,
pixclk             75 drivers/video/fbdev/broadsheetfb.c 		.pixclk = 14,
pixclk             87 drivers/video/fbdev/broadsheetfb.c 		.pixclk = 3,
pixclk            801 drivers/video/fbdev/broadsheetfb.c 	args[4] = panel_table[par->panel_index].pixclk;
pixclk            472 drivers/video/fbdev/fb-puv3.c 	u32 pixclk = 0;
pixclk            484 drivers/video/fbdev/fb-puv3.c 			pixclk = unifb_modes[i].pixclock;
pixclk            494 drivers/video/fbdev/fb-puv3.c 	if (pixclk != 0) {
pixclk            495 drivers/video/fbdev/fb-puv3.c 		if (clk_set_rate(clk_vga, pixclk)) { /* set clock failed */
pixclk            344 drivers/video/fbdev/s3c-fb.c static int s3c_fb_calc_pixclk(struct s3c_fb *sfb, unsigned int pixclk)
pixclk            356 drivers/video/fbdev/s3c-fb.c 	tmp *= pixclk;
pixclk            362 drivers/video/fbdev/s3c-fb.c 		pixclk, clk, result, result ? clk / result : clk);
pixclk           1059 drivers/video/fbdev/s3c-fb.c 	u64 pixclk = 1000000000000ULL;
pixclk           1068 drivers/video/fbdev/s3c-fb.c 	do_div(pixclk, div);
pixclk           1070 drivers/video/fbdev/s3c-fb.c 	mode->pixclock = pixclk;
pixclk             98 drivers/video/fbdev/s3c2410fb.c 					  unsigned long pixclk)
pixclk            108 drivers/video/fbdev/s3c2410fb.c 	div = (unsigned long long)clk * pixclk;
pixclk            112 drivers/video/fbdev/s3c2410fb.c 	dprintk("pixclk %ld, divisor is %ld\n", pixclk, (long)div);