pix_clk_post_divider  240 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 		pll_settings->pix_clk_post_divider = post_divider;
pix_clk_post_divider  309 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 	if (pll_settings->pix_clk_post_divider) {
pix_clk_post_divider  310 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 		min_post_divider = pll_settings->pix_clk_post_divider;
pix_clk_post_divider  311 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 		max_post_divider = pll_settings->pix_clk_post_divider;
pix_clk_post_divider  454 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 		pll_settings->pix_clk_post_divider =
pix_clk_post_divider  870 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 			pll_settings->pix_clk_post_divider;
pix_clk_post_divider  115 drivers/gpu/drm/amd/display/dc/inc/clock_source.h 	uint32_t pix_clk_post_divider;