pix_clk_params    180 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c 		if (pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10 > max_pix_clk)
pix_clk_params    181 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c 			max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10;
pix_clk_params    187 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c 				pipe_ctx->stream_res.pix_clk_params.requested_sym_clk > max_pix_clk)
pix_clk_params    188 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c 			max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_sym_clk;
pix_clk_params   1492 drivers/gpu/drm/amd/display/dc/core/dc_link.c 	pipe_ctx->stream_res.pix_clk_params.requested_sym_clk =
pix_clk_params   2440 drivers/gpu/drm/amd/display/dc/core/dc_link.c 	bpc = get_color_depth(pipe_ctx->stream_res.pix_clk_params.color_depth);
pix_clk_params     90 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 				pipes[i].stream_res.pix_clk_params.requested_pix_clk_100hz =
pix_clk_params     94 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 							&pipes[i].stream_res.pix_clk_params,
pix_clk_params    199 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 		if (pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10 > max_pix_clk)
pix_clk_params    200 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 			max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10;
pix_clk_params    206 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 				pipe_ctx->stream_res.pix_clk_params.requested_sym_clk > max_pix_clk)
pix_clk_params    207 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c 			max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_sym_clk;
pix_clk_params    397 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 		struct pixel_clk_params *pix_clk_params,
pix_clk_params    405 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 	switch (pix_clk_params->signal_type) {
pix_clk_params    407 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 		requested_clk_100hz = pix_clk_params->requested_pix_clk_100hz;
pix_clk_params    408 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 		if (pix_clk_params->pixel_encoding != PIXEL_ENCODING_YCBCR422) {
pix_clk_params    409 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 			switch (pix_clk_params->color_depth) {
pix_clk_params    430 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 		requested_clk_100hz = pix_clk_params->requested_sym_clk * 10;
pix_clk_params    431 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 		actual_pix_clk_100hz = pix_clk_params->requested_pix_clk_100hz;
pix_clk_params    435 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 		requested_clk_100hz = pix_clk_params->requested_pix_clk_100hz;
pix_clk_params    436 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 		actual_pix_clk_100hz = pix_clk_params->requested_pix_clk_100hz;
pix_clk_params    442 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 		encoder_object_id = pix_clk_params->encoder_object_id;
pix_clk_params    443 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 	bp_adjust_pixel_clock_params.signal_type = pix_clk_params->signal_type;
pix_clk_params    445 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 		ss_enable = pix_clk_params->flags.ENABLE_SS;
pix_clk_params    477 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 		struct pixel_clk_params *pix_clk_params)
pix_clk_params    492 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 	if ((pix_clk_params->flags.ENABLE_SS) ||
pix_clk_params    493 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 			(dc_is_dp_signal(pix_clk_params->signal_type))) {
pix_clk_params    497 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 					pix_clk_params->signal_type,
pix_clk_params    505 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 	if (!pll_adjust_pix_clk(clk_src, pix_clk_params, pll_settings)) {
pix_clk_params    511 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 				pix_clk_params->requested_pix_clk_100hz;
pix_clk_params    513 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 				pix_clk_params->requested_pix_clk_100hz;
pix_clk_params    515 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 		if (dc_is_dp_signal(pix_clk_params->signal_type))
pix_clk_params    520 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 	if (pix_clk_params->signal_type == SIGNAL_TYPE_HDMI_TYPE_A)
pix_clk_params    539 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 		struct pixel_clk_params *pix_clk_params)
pix_clk_params    543 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 	actual_pixel_clock_100hz = pix_clk_params->requested_pix_clk_100hz;
pix_clk_params    545 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 	if (pix_clk_params->signal_type == SIGNAL_TYPE_HDMI_TYPE_A) {
pix_clk_params    546 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 		switch (pix_clk_params->color_depth) {
pix_clk_params    562 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 	pll_settings->calculated_pix_clk_100hz = pix_clk_params->requested_pix_clk_100hz;
pix_clk_params    567 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 		struct pixel_clk_params *pix_clk_params,
pix_clk_params    574 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 	if (pix_clk_params == NULL || pll_settings == NULL
pix_clk_params    575 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 			|| pix_clk_params->requested_pix_clk_100hz == 0) {
pix_clk_params    588 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 					pix_clk_params->requested_pix_clk_100hz;
pix_clk_params    593 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 			pll_settings, pix_clk_params);
pix_clk_params    600 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 		struct pixel_clk_params *pix_clk_params,
pix_clk_params    606 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 	if (pix_clk_params == NULL || pll_settings == NULL
pix_clk_params    607 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 			|| pix_clk_params->requested_pix_clk_100hz == 0) {
pix_clk_params    620 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 					pix_clk_params->requested_pix_clk_100hz;
pix_clk_params    625 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 			pll_settings, pix_clk_params);
pix_clk_params    843 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 		struct pixel_clk_params *pix_clk_params,
pix_clk_params    854 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 			!dc_is_dp_signal(pix_clk_params->signal_type) &&
pix_clk_params    859 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 	bp_pc_params.controller_id = pix_clk_params->controller_id;
pix_clk_params    862 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 	bp_pc_params.encoder_object_id = pix_clk_params->encoder_object_id;
pix_clk_params    863 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 	bp_pc_params.signal_type = pix_clk_params->signal_type;
pix_clk_params    883 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 			&& !dc_is_dp_signal(pix_clk_params->signal_type)) {
pix_clk_params    885 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 		if (pix_clk_params->flags.ENABLE_SS)
pix_clk_params    887 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 							pix_clk_params->signal_type,
pix_clk_params    893 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 					pix_clk_params->signal_type,
pix_clk_params    894 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 					pix_clk_params->color_depth);
pix_clk_params    902 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 		struct pixel_clk_params *pix_clk_params,
pix_clk_params    910 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 		unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;
pix_clk_params    928 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 			!dc_is_dp_signal(pix_clk_params->signal_type) &&
pix_clk_params    933 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 	bp_pc_params.controller_id = pix_clk_params->controller_id;
pix_clk_params    936 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 	bp_pc_params.encoder_object_id = pix_clk_params->encoder_object_id;
pix_clk_params    937 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 	bp_pc_params.signal_type = pix_clk_params->signal_type;
pix_clk_params    944 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 		if (pix_clk_params->flags.SUPPORT_YCBCR420) {
pix_clk_params    954 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 					pix_clk_params->signal_type,
pix_clk_params    955 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 					pix_clk_params->color_depth,
pix_clk_params    956 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 					pix_clk_params->flags.SUPPORT_YCBCR420);
pix_clk_params   1053 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 		struct pixel_clk_params *pix_clk_params,
pix_clk_params   1056 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 	dce112_program_pix_clk(clock_source, pix_clk_params, pll_settings);
pix_clk_params   1154 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 			pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz;
pix_clk_params   1157 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 			pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz;
pix_clk_params   1163 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		if (pipe_ctx->stream_res.pix_clk_params.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
pix_clk_params   1167 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 					pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz/2;
pix_clk_params   1296 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 				&pipe_ctx->stream_res.pix_clk_params,
pix_clk_params    846 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 	get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);
pix_clk_params    849 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 		&pipe_ctx->stream_res.pix_clk_params,
pix_clk_params    756 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			&pipe_ctx->stream_res.pix_clk_params,
pix_clk_params    432 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 		pix_clk = dc->current_state->res_ctx.pipe_ctx[i].stream_res.pix_clk_params.requested_pix_clk_100hz / 10;
pix_clk_params   1023 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);
pix_clk_params   1027 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 		&pipe_ctx->stream_res.pix_clk_params,
pix_clk_params    562 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 			&pipe_ctx->stream_res.pix_clk_params,
pix_clk_params   1481 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);
pix_clk_params   1485 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		&pipe_ctx->stream_res.pix_clk_params,
pix_clk_params    245 drivers/gpu/drm/amd/display/dc/inc/core_types.h 	struct pixel_clk_params pix_clk_params;