pix_clk 630 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c uint32_t pix_clk, pix_clk 633 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c bool over_340_mhz = pix_clk > 340000 ? 1 : 0; pix_clk 1809 drivers/gpu/drm/amd/display/dc/core/dc_resource.c uint32_t pix_clk = timing->pix_clk_100hz; pix_clk 1810 drivers/gpu/drm/amd/display/dc/core/dc_resource.c uint32_t normalized_pix_clk = pix_clk; pix_clk 1813 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pix_clk /= 2; pix_clk 1818 drivers/gpu/drm/amd/display/dc/core/dc_resource.c normalized_pix_clk = pix_clk; pix_clk 1821 drivers/gpu/drm/amd/display/dc/core/dc_resource.c normalized_pix_clk = (pix_clk * 30) / 24; pix_clk 1824 drivers/gpu/drm/amd/display/dc/core/dc_resource.c normalized_pix_clk = (pix_clk * 36) / 24; pix_clk 1827 drivers/gpu/drm/amd/display/dc/core/dc_resource.c normalized_pix_clk = (pix_clk * 48) / 24; pix_clk 429 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c int pix_clk = 0; pix_clk 432 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c pix_clk = dc->current_state->res_ctx.pipe_ctx[i].stream_res.pix_clk_params.requested_pix_clk_100hz / 10; pix_clk 457 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c pix_clk); pix_clk 107 drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h uint32_t pix_clk, pix_clk 61 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c clk_disable_unprepare(fsl_dev->pix_clk); pix_clk 70 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c clk_prepare_enable(fsl_dev->pix_clk); pix_clk 89 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c clk_set_rate(fsl_dev->pix_clk, mode->clock * 1000); pix_clk 305 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c fsl_dev->pix_clk = clk_register_divider(dev, pix_clk_name, pix_clk 308 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c if (IS_ERR(fsl_dev->pix_clk)) { pix_clk 310 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c ret = PTR_ERR(fsl_dev->pix_clk); pix_clk 339 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c clk_unregister(fsl_dev->pix_clk); pix_clk 352 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c clk_unregister(fsl_dev->pix_clk); pix_clk 185 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h struct clk *pix_clk; pix_clk 165 drivers/gpu/drm/ingenic/ingenic-drm.c struct clk *lcd_clk, *pix_clk; pix_clk 328 drivers/gpu/drm/ingenic/ingenic-drm.c rate = clk_round_rate(priv->pix_clk, pix_clk 351 drivers/gpu/drm/ingenic/ingenic-drm.c clk_set_rate(priv->pix_clk, state->adjusted_mode.clock * 1000); pix_clk 669 drivers/gpu/drm/ingenic/ingenic-drm.c priv->pix_clk = devm_clk_get(dev, "lcd_pclk"); pix_clk 670 drivers/gpu/drm/ingenic/ingenic-drm.c if (IS_ERR(priv->pix_clk)) { pix_clk 672 drivers/gpu/drm/ingenic/ingenic-drm.c return PTR_ERR(priv->pix_clk); pix_clk 752 drivers/gpu/drm/ingenic/ingenic-drm.c ret = clk_prepare_enable(priv->pix_clk); pix_clk 796 drivers/gpu/drm/ingenic/ingenic-drm.c clk_disable_unprepare(priv->pix_clk); pix_clk 806 drivers/gpu/drm/ingenic/ingenic-drm.c clk_disable_unprepare(priv->pix_clk); pix_clk 218 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c static int pll_calculate(unsigned long pix_clk, unsigned long ref_clk, pix_clk 237 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c bclk = ((u64)pix_clk) * 10; pix_clk 240 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c tmds_clk = pix_clk >> 2; pix_clk 242 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c tmds_clk = pix_clk; pix_clk 272 drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c DBG("pix_clk: %lu", pix_clk); pix_clk 3151 drivers/gpu/drm/radeon/r100.c fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff; pix_clk 3268 drivers/gpu/drm/radeon/r100.c pix_clk.full = 0; pix_clk 3273 drivers/gpu/drm/radeon/r100.c pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */ pix_clk 3274 drivers/gpu/drm/radeon/r100.c pix_clk.full = dfixed_div(pix_clk, temp_ff); pix_clk 3276 drivers/gpu/drm/radeon/r100.c peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff); pix_clk 3479 drivers/gpu/drm/radeon/r100.c disp_drain_rate.full = dfixed_div(pix_clk, temp_ff); pix_clk 55 drivers/gpu/drm/sti/sti_crtc.c struct clk *compo_clk, *pix_clk; pix_clk 65 drivers/gpu/drm/sti/sti_crtc.c pix_clk = compo->clk_pix_main; pix_clk 68 drivers/gpu/drm/sti/sti_crtc.c pix_clk = compo->clk_pix_aux; pix_clk 78 drivers/gpu/drm/sti/sti_crtc.c if (clk_set_rate(pix_clk, rate) < 0) { pix_clk 82 drivers/gpu/drm/sti/sti_crtc.c if (clk_prepare_enable(pix_clk)) { pix_clk 97 drivers/gpu/drm/sti/sti_crtc.c clk_disable_unprepare(pix_clk); pix_clk 608 drivers/gpu/ipu-v3/ipu-csi.c u32 pix_clk) pix_clk 623 drivers/gpu/ipu-v3/ipu-csi.c ipu_csi_set_testgen_mclk(csi, pix_clk, ipu_clk); pix_clk 1367 drivers/media/i2c/adv7604.c u32 pix_clk; pix_clk 1382 drivers/media/i2c/adv7604.c pix_clk = hfreq * htotal(bt); pix_clk 1384 drivers/media/i2c/adv7604.c if ((pix_clk < bt->pixelclock + 1000000) && pix_clk 1385 drivers/media/i2c/adv7604.c (pix_clk > bt->pixelclock - 1000000)) { pix_clk 1421 drivers/media/i2c/adv7842.c u32 pix_clk; pix_clk 1436 drivers/media/i2c/adv7842.c pix_clk = hfreq * htotal(bt); pix_clk 1438 drivers/media/i2c/adv7842.c if ((pix_clk < bt->pixelclock + 1000000) && pix_clk 1439 drivers/media/i2c/adv7842.c (pix_clk > bt->pixelclock - 1000000)) { pix_clk 480 drivers/media/v4l2-core/v4l2-dv-timings.c unsigned pix_clk; pix_clk 575 drivers/media/v4l2-core/v4l2-dv-timings.c pix_clk = (image_width + h_blank) * hfreq; pix_clk 576 drivers/media/v4l2-core/v4l2-dv-timings.c pix_clk = (pix_clk / clk_gran) * clk_gran; pix_clk 595 drivers/media/v4l2-core/v4l2-dv-timings.c pix_clk = (image_width + h_blank) * hfreq; pix_clk 596 drivers/media/v4l2-core/v4l2-dv-timings.c pix_clk = (pix_clk / CVT_PXL_CLK_GRAN) * CVT_PXL_CLK_GRAN; pix_clk 630 drivers/media/v4l2-core/v4l2-dv-timings.c fmt->bt.pixelclock = pix_clk; pix_clk 694 drivers/media/v4l2-core/v4l2-dv-timings.c int pix_clk; pix_clk 756 drivers/media/v4l2-core/v4l2-dv-timings.c pix_clk = (image_width + h_blank) * hfreq; pix_clk 757 drivers/media/v4l2-core/v4l2-dv-timings.c pix_clk = pix_clk / GTF_PXL_CLK_GRAN * GTF_PXL_CLK_GRAN; pix_clk 788 drivers/media/v4l2-core/v4l2-dv-timings.c fmt->bt.pixelclock = pix_clk; pix_clk 41 drivers/staging/media/imx/imx6-mipi-csi2.c struct clk *pix_clk; /* what is this? */ pix_clk 300 drivers/staging/media/imx/imx6-mipi-csi2.c ret = clk_prepare_enable(csi2->pix_clk); pix_clk 337 drivers/staging/media/imx/imx6-mipi-csi2.c clk_disable_unprepare(csi2->pix_clk); pix_clk 347 drivers/staging/media/imx/imx6-mipi-csi2.c clk_disable_unprepare(csi2->pix_clk); pix_clk 609 drivers/staging/media/imx/imx6-mipi-csi2.c csi2->pix_clk = devm_clk_get(&pdev->dev, "pix"); pix_clk 610 drivers/staging/media/imx/imx6-mipi-csi2.c if (IS_ERR(csi2->pix_clk)) { pix_clk 612 drivers/staging/media/imx/imx6-mipi-csi2.c ret = PTR_ERR(csi2->pix_clk); pix_clk 750 drivers/video/fbdev/omap/hwa742.c unsigned long *sys_clk, unsigned long *pix_clk) pix_clk 766 drivers/video/fbdev/omap/hwa742.c *pix_clk = *sys_clk / pix_div; /* HZ */ pix_clk 771 drivers/video/fbdev/omap/hwa742.c *sys_clk, *pix_clk); pix_clk 775 drivers/video/fbdev/omap/hwa742.c static int setup_tearsync(unsigned long pix_clk, int extif_div) pix_clk 817 drivers/video/fbdev/omap/hwa742.c hwa742.line_upd_time = (hdisp + hndp) * 1000000 / (pix_clk / 1000); pix_clk 853 drivers/video/fbdev/omap/hwa742.c hs = hs * 1000000 / (pix_clk / 1000); /* ps */ pix_clk 856 drivers/video/fbdev/omap/hwa742.c vs = vs * (hdisp + hndp) * 1000000 / (pix_clk / 1000); /* ps */ pix_clk 876 drivers/video/fbdev/omap/hwa742.c pix_clk, hwa742.pix_tx_time, hwa742.line_upd_time); pix_clk 927 drivers/video/fbdev/omap/hwa742.c unsigned long sys_clk, pix_clk; pix_clk 955 drivers/video/fbdev/omap/hwa742.c calc_hwa742_clk_rates(ext_clk, &sys_clk, &pix_clk); pix_clk 975 drivers/video/fbdev/omap/hwa742.c if ((r = setup_tearsync(pix_clk, extif_mem_div)) < 0) { pix_clk 368 include/video/imx-ipu-v3.h u32 pix_clk);