pir_reg 96 arch/powerpc/boot/treeboot-akebono.c u32 pir_reg; pir_reg 141 arch/powerpc/boot/treeboot-akebono.c pir_reg = mfspr(SPRN_PIR); pir_reg 155 arch/powerpc/boot/treeboot-akebono.c fdt_set_boot_cpuid_phys(_dtb_start, pir_reg); pir_reg 83 arch/powerpc/boot/treeboot-currituck.c u32 pir_reg; pir_reg 97 arch/powerpc/boot/treeboot-currituck.c pir_reg = mfspr(SPRN_PIR); pir_reg 111 arch/powerpc/boot/treeboot-currituck.c fdt_set_boot_cpuid_phys(_dtb_start, pir_reg); pir_reg 63 arch/powerpc/boot/treeboot-iss4xx.c u32 pir_reg; pir_reg 69 arch/powerpc/boot/treeboot-iss4xx.c pir_reg = mfspr(SPRN_PIR); pir_reg 70 arch/powerpc/boot/treeboot-iss4xx.c fdt_set_boot_cpuid_phys(_dtb_start, pir_reg); pir_reg 1012 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c u64 cir_reg = 0, pir_reg = 0; pir_reg 1018 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c pir_reg = 0; /* PIR not available at TL1 */ pir_reg 1022 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c pir_reg = NIX_AF_TL2X_PIR(schq); pir_reg 1026 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c pir_reg = NIX_AF_TL3X_PIR(schq); pir_reg 1030 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c pir_reg = NIX_AF_TL4X_PIR(schq); pir_reg 1039 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c if (!pir_reg) pir_reg 1041 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c cfg = rvu_read64(rvu, blkaddr, pir_reg); pir_reg 1042 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c rvu_write64(rvu, blkaddr, pir_reg, cfg & ~BIT_ULL(0));