pir 633 arch/powerpc/include/asm/opal-api.h __be32 pir; /* for CHECKSTOP_TYPE_CORE */ pir 210 arch/powerpc/include/uapi/asm/kvm.h __u32 pir; /* read-only */ pir 59 arch/powerpc/include/uapi/asm/kvm_para.h __u32 pir; pir 527 arch/powerpc/kernel/kvm.c kvm_patch_ins_lwz(inst, magic_var(pir), inst_rt); pir 490 arch/powerpc/kernel/sysfs.c SYSFS_SPRSETUP(pir, SPRN_PIR); pir 501 arch/powerpc/kernel/sysfs.c static DEVICE_ATTR(pir, 0400, show_pir, NULL); pir 1387 arch/powerpc/kvm/booke.c vcpu->arch.shared->pir = vcpu->vcpu_id; pir 1540 arch/powerpc/kvm/booke.c sregs->u.e.pir = vcpu->vcpu_id; pir 1553 arch/powerpc/kvm/booke.c if (sregs->u.e.pir != vcpu->vcpu_id) pir 67 arch/powerpc/kvm/e500_emulate.c int pir = param & PPC_DBELL_PIR_MASK; pir 75 arch/powerpc/kvm/e500_emulate.c int cpir = cvcpu->arch.shared->pir; pir 76 arch/powerpc/kvm/e500_emulate.c if ((param & PPC_DBELL_MSG_BRDCAST) || (cpir == pir)) { pir 218 arch/powerpc/kvm/mpic.c uint32_t pir; /* Processor initialization register */ pir 522 arch/powerpc/kvm/mpic.c opp->pir = 0; pir 40 arch/powerpc/platforms/85xx/smp.c u32 pir; pir 250 arch/powerpc/platforms/85xx/smp.c out_be32(&spin_table->pir, hw_cpu); pir 84 arch/powerpc/platforms/powernv/idle.c uint64_t pir = get_hard_smp_processor_id(cpu); pir 87 arch/powerpc/platforms/powernv/idle.c rc = opal_slw_set_reg(pir, SPRN_HSPRG0, hsprg0_val); pir 91 arch/powerpc/platforms/powernv/idle.c rc = opal_slw_set_reg(pir, SPRN_LPCR, lpcr_val); pir 96 arch/powerpc/platforms/powernv/idle.c rc = opal_slw_set_reg(pir, P9_STOP_SPR_MSR, msr_val); pir 100 arch/powerpc/platforms/powernv/idle.c rc = opal_slw_set_reg(pir, pir 110 arch/powerpc/platforms/powernv/idle.c rc = opal_slw_set_reg(pir, SPRN_HMEER, hmeer_val); pir 114 arch/powerpc/platforms/powernv/idle.c rc = opal_slw_set_reg(pir, SPRN_HID0, hid0_val); pir 121 arch/powerpc/platforms/powernv/idle.c rc = opal_slw_set_reg(pir, SPRN_HID1, hid1_val); pir 125 arch/powerpc/platforms/powernv/idle.c rc = opal_slw_set_reg(pir, SPRN_HID4, hid4_val); pir 129 arch/powerpc/platforms/powernv/idle.c rc = opal_slw_set_reg(pir, SPRN_HID5, hid5_val); pir 951 arch/powerpc/platforms/powernv/idle.c u64 pir = get_hard_smp_processor_id(cpu); pir 960 arch/powerpc/platforms/powernv/idle.c opal_slw_set_reg(pir, SPRN_LPCR, lpcr_val); pir 110 arch/powerpc/platforms/powernv/opal-core.c static void fill_prstatus(struct elf_prstatus *prstatus, int pir, pir 121 arch/powerpc/platforms/powernv/opal-core.c prstatus->pr_pid = cpu_to_be32(100 + pir); pir 128 arch/powerpc/platforms/powernv/opal-core.c if (pir == oc_conf->crashing_cpu) { pir 259 arch/powerpc/platforms/powernv/opal-core.c thread_pir = be32_to_cpu(thdr->pir); pir 454 arch/powerpc/platforms/powernv/opal-fadump.c thread_pir = be32_to_cpu(thdr->pir); pir 59 arch/powerpc/platforms/powernv/opal-fadump.h __be32 pir; pir 80 arch/powerpc/platforms/powernv/opal-hmi.c be32_to_cpu(hmi_evt->u.xstop_error.u.pir)); pir 1908 arch/powerpc/sysdev/mpic.c u32 pir; pir 1913 arch/powerpc/sysdev/mpic.c pir = mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT)); pir 1914 arch/powerpc/sysdev/mpic.c pir |= (1 << cpuid); pir 1915 arch/powerpc/sysdev/mpic.c mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir); pir 1919 arch/powerpc/sysdev/mpic.c pir &= ~(1 << cpuid); pir 1920 arch/powerpc/sysdev/mpic.c mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir); pir 385 arch/x86/kvm/lapic.c bool __kvm_apic_update_irr(u32 *pir, void *regs, int *max_irr) pir 395 arch/x86/kvm/lapic.c pir_val = READ_ONCE(pir[i]); pir 399 arch/x86/kvm/lapic.c irr_val |= xchg(&pir[i], 0); pir 415 arch/x86/kvm/lapic.c bool kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir, int *max_irr) pir 419 arch/x86/kvm/lapic.c return __kvm_apic_update_irr(pir, apic->regs, max_irr); pir 87 arch/x86/kvm/lapic.h bool __kvm_apic_update_irr(u32 *pir, void *regs, int *max_irr); pir 88 arch/x86/kvm/lapic.h bool kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir, int *max_irr); pir 3420 arch/x86/kvm/vmx/nested.c max_irr = find_last_bit((unsigned long *)vmx->nested.pi_desc->pir, 256); pir 3426 arch/x86/kvm/vmx/nested.c __kvm_apic_update_irr(vmx->nested.pi_desc->pir, pir 6148 arch/x86/kvm/vmx/vmx.c kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr); pir 6195 arch/x86/kvm/vmx/vmx.c memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir)); pir 49 arch/x86/kvm/vmx/vmx.h u32 pir[8]; /* Posted interrupt requested */ pir 356 arch/x86/kvm/vmx/vmx.h return test_and_set_bit(vector, (unsigned long *)pi_desc->pir); pir 361 arch/x86/kvm/vmx/vmx.h return bitmap_empty((unsigned long *)pi_desc->pir, NR_VECTORS); pir 55 drivers/net/can/grcan.c u32 pir; /* 0x10C */ pir 991 drivers/net/can/grcan.c grcan_read_reg(®s->pir); pir 990 drivers/net/ethernet/freescale/enetc/enetc.c cbdr->pir = hw->reg + ENETC_SICBDRPIR; pir 95 drivers/net/ethernet/freescale/enetc/enetc.h void __iomem *pir; pir 57 drivers/net/ethernet/freescale/enetc/enetc_cbdr.c enetc_wr_reg(ring->pir, i); pir 38 drivers/net/ethernet/mscc/ocelot_police.c u32 pir; /* PIR in kbps/fps */ pir 47 drivers/net/ethernet/mscc/ocelot_police.c u32 cir = 0, cbs = 0, pir = 0, pbs = 0; pir 54 drivers/net/ethernet/mscc/ocelot_police.c pir = conf->pir; pir 81 drivers/net/ethernet/mscc/ocelot_police.c pir += conf->cir; pir 84 drivers/net/ethernet/mscc/ocelot_police.c if (pir == 0 && pbs == 0) { pir 88 drivers/net/ethernet/mscc/ocelot_police.c pir = DIV_ROUND_UP(pir, 100); pir 89 drivers/net/ethernet/mscc/ocelot_police.c pir *= 3; /* 33 1/3 kbps */ pir 96 drivers/net/ethernet/mscc/ocelot_police.c if (pir >= 100) { pir 98 drivers/net/ethernet/mscc/ocelot_police.c pir = DIV_ROUND_UP(pir, 100); pir 99 drivers/net/ethernet/mscc/ocelot_police.c pir *= 3; /* 33 1/3 fps */ pir 105 drivers/net/ethernet/mscc/ocelot_police.c if (pir == 0 && pbs == 0) { pir 110 drivers/net/ethernet/mscc/ocelot_police.c pir *= 3; /* 1/3 fps */ pir 119 drivers/net/ethernet/mscc/ocelot_police.c pir = GENMASK(15, 0); pir 125 drivers/net/ethernet/mscc/ocelot_police.c if (pir > GENMASK(15, 0)) { pir 154 drivers/net/ethernet/mscc/ocelot_police.c ANA_POL_PIR_CFG_PIR_RATE(pir) | pir 185 drivers/net/ethernet/mscc/ocelot_police.c pp.pir = pol->rate; pir 190 drivers/net/ethernet/mscc/ocelot_police.c __func__, port->chip_port, pp.pir, pp.pbs); pir 48 drivers/net/ethernet/netronome/nfp/flower/qos_conf.c __be32 pir; pir 123 drivers/net/ethernet/netronome/nfp/flower/qos_conf.c config->pir = cpu_to_be32(rate); pir 1214 drivers/net/ethernet/renesas/sh_eth.c u32 pir; pir 1219 drivers/net/ethernet/renesas/sh_eth.c pir = ioread32(bitbang->addr); pir 1221 drivers/net/ethernet/renesas/sh_eth.c pir |= mask; pir 1223 drivers/net/ethernet/renesas/sh_eth.c pir &= ~mask; pir 1224 drivers/net/ethernet/renesas/sh_eth.c iowrite32(pir, bitbang->addr); pir 210 tools/arch/powerpc/include/uapi/asm/kvm.h __u32 pir; /* read-only */