pipeline 1065 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c if (c->pipeline->dual_link) { pipeline 547 drivers/gpu/drm/arm/display/komeda/komeda_crtc.c if (kplane->layer->base.pipeline == crtc->master) pipeline 154 drivers/gpu/drm/arm/display/komeda/komeda_pipeline.c return komeda_pipeline_get_first_component(c->pipeline, avail_inputs); pipeline 203 drivers/gpu/drm/arm/display/komeda/komeda_pipeline.c c->pipeline = pipe; pipeline 269 drivers/gpu/drm/arm/display/komeda/komeda_pipeline.c struct komeda_pipeline *pipe = c->pipeline; pipeline 334 drivers/gpu/drm/arm/display/komeda/komeda_pipeline.c return slave ? slave->pipeline : NULL; pipeline 82 drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h struct komeda_pipeline *pipeline; pipeline 502 drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h return komeda_pipeline_get_first_component(c->pipeline, avail_inputs); pipeline 104 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c WARN_ON(!drm_modeset_is_locked(&c->pipeline->obj.lock)); pipeline 160 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c pipe_st = komeda_pipeline_get_state_and_set_crtc(c->pipeline, pipeline 261 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c pipe_st = komeda_pipeline_get_state(c->pipeline, state); pipeline 471 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c struct komeda_pipeline *pipe = scaler->base.pipeline; pipeline 578 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c komeda_split_data_flow(splitter->base.pipeline->scalers[0], pipeline 791 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c struct komeda_scaler *scaler = layer->base.pipeline->scalers[0]; pipeline 836 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c struct komeda_pipeline *pipe = layer->base.pipeline; pipeline 1039 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c struct komeda_pipeline *pipe = left->base.pipeline; pipeline 1107 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c struct komeda_pipeline *pipe = wb_layer->base.pipeline; pipeline 23 drivers/gpu/drm/arm/display/komeda/komeda_plane.c struct komeda_pipeline *pipe = kplane->layer->base.pipeline; pipeline 269 drivers/gpu/drm/arm/display/komeda/komeda_plane.c get_possible_crtcs(kms, c->pipeline), pipeline 313 drivers/gpu/drm/arm/display/komeda/komeda_plane.c komeda_set_crtc_plane_mask(kms, c->pipeline, plane); pipeline 25 drivers/gpu/drm/arm/display/komeda/komeda_wb_connector.c dflow->input.component = &wb_layer->base.pipeline->compiz->base; pipeline 299 drivers/gpu/drm/i915/gvt/cmd_parser.c #define OP_MFX(pipeline, op, sub_opa, sub_opb) \ pipeline 301 drivers/gpu/drm/i915/gvt/cmd_parser.c (pipeline) << 11 | \ pipeline 353 drivers/gpu/drm/i915/gvt/cmd_parser.c #define OP_VEB(pipeline, op, sub_opa, sub_opb) \ pipeline 355 drivers/gpu/drm/i915/gvt/cmd_parser.c (pipeline) << 11 | \ pipeline 139 drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c struct mdp5_pipeline *pipeline = mdp5_crtc_get_pipeline(encoder->crtc); pipeline 146 drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c mdp5_ctl_set_encoder_state(ctl, pipeline, false); pipeline 147 drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c mdp5_ctl_commit(ctl, pipeline, mdp_ctl_flush_mask_encoder(intf), true); pipeline 159 drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c struct mdp5_pipeline *pipeline = mdp5_crtc_get_pipeline(encoder->crtc); pipeline 168 drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c mdp5_ctl_commit(ctl, pipeline, mdp_ctl_flush_mask_encoder(intf), true); pipeline 170 drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c mdp5_ctl_set_encoder_state(ctl, pipeline, true); pipeline 91 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline; pipeline 98 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c return mdp5_ctl_commit(ctl, pipeline, flush_mask, start); pipeline 123 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c mixer = mdp5_cstate->pipeline.mixer; pipeline 126 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c r_mixer = mdp5_cstate->pipeline.r_mixer; pipeline 137 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline; pipeline 155 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c mdp5_ctl_blend(ctl, pipeline, NULL, NULL, 0, 0); pipeline 214 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline; pipeline 220 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c struct mdp5_hw_mixer *mixer = pipeline->mixer; pipeline 222 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c struct mdp5_hw_mixer *r_mixer = pipeline->r_mixer; pipeline 356 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c mdp5_ctl_blend(ctl, pipeline, stage, r_stage, plane_cnt, pipeline 367 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c struct mdp5_hw_mixer *mixer = mdp5_cstate->pipeline.mixer; pipeline 368 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c struct mdp5_hw_mixer *r_mixer = mdp5_cstate->pipeline.r_mixer; pipeline 448 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c struct mdp5_interface *intf = mdp5_cstate->pipeline.intf; pipeline 485 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c &mdp5_cstate->pipeline, 0, true); pipeline 488 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c &mdp5_cstate->pipeline, 0, false); pipeline 511 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline; pipeline 515 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c new_mixer = !pipeline->mixer; pipeline 517 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c if ((need_right_mixer && !pipeline->r_mixer) || pipeline 518 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c (!need_right_mixer && pipeline->r_mixer)) pipeline 522 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c struct mdp5_hw_mixer *old_mixer = pipeline->mixer; pipeline 523 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c struct mdp5_hw_mixer *old_r_mixer = pipeline->r_mixer; pipeline 532 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c &pipeline->mixer, need_right_mixer ? pipeline 533 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c &pipeline->r_mixer : NULL); pipeline 541 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c pipeline->r_mixer = NULL; pipeline 549 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c intf = pipeline->intf; pipeline 552 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c mdp5_cstate->vblank_irqmask = intf2vblank(pipeline->mixer, intf); pipeline 556 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c mdp5_cstate->pp_done_irqmask = lm2ppdone(pipeline->mixer); pipeline 598 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c if (mdp5_cstate->pipeline.r_mixer) pipeline 801 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c lm = mdp5_cstate->pipeline.mixer->lm; pipeline 861 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline; pipeline 889 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c if (mdp5_cstate->pipeline.r_mixer) pipeline 923 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c ret = mdp5_ctl_set_cursor(ctl, pipeline, 0, cursor_enable); pipeline 960 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c if (mdp5_cstate->pipeline.r_mixer) pipeline 991 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline; pipeline 994 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c if (WARN_ON(!pipeline)) pipeline 1000 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c drm_printf(p, "\thwmixer=%s\n", pipeline->mixer ? pipeline 1001 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c pipeline->mixer->name : "(null)"); pipeline 1004 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c drm_printf(p, "\tright hwmixer=%s\n", pipeline->r_mixer ? pipeline 1005 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c pipeline->r_mixer->name : "(null)"); pipeline 1116 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c mdp5_cstate->pipeline.mixer->lm); pipeline 1161 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c mdp5_ctl_set_pipeline(mdp5_cstate->ctl, &mdp5_cstate->pipeline); pipeline 1180 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c return WARN_ON(!mdp5_cstate->pipeline.mixer) ? pipeline 1181 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c ERR_PTR(-EINVAL) : mdp5_cstate->pipeline.mixer; pipeline 1193 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c return &mdp5_cstate->pipeline; pipeline 135 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c static void set_ctl_op(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline) pipeline 138 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c struct mdp5_interface *intf = pipeline->intf; pipeline 159 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c if (pipeline->r_mixer) pipeline 168 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c int mdp5_ctl_set_pipeline(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline) pipeline 171 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c struct mdp5_interface *intf = pipeline->intf; pipeline 177 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c set_ctl_op(ctl, pipeline); pipeline 183 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c struct mdp5_pipeline *pipeline) pipeline 185 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c struct mdp5_interface *intf = pipeline->intf; pipeline 225 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c struct mdp5_pipeline *pipeline, pipeline 228 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c struct mdp5_interface *intf = pipeline->intf; pipeline 236 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c if (start_signal_needed(ctl, pipeline)) { pipeline 248 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c int mdp5_ctl_set_cursor(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline, pipeline 254 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c struct mdp5_hw_mixer *mixer = pipeline->mixer; pipeline 262 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c if (pipeline->r_mixer) { pipeline 347 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c int mdp5_ctl_blend(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline, pipeline 352 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c struct mdp5_hw_mixer *mixer = pipeline->mixer; pipeline 353 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c struct mdp5_hw_mixer *r_mixer = pipeline->r_mixer; pipeline 470 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c static u32 fix_sw_flush(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline, pipeline 480 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c sw_mask |= mdp_ctl_flush_mask_lm(pipeline->mixer->lm); pipeline 527 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c struct mdp5_pipeline *pipeline, pipeline 542 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c flush_mask |= fix_sw_flush(ctl, pipeline, flush_mask); pipeline 564 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c if (start_signal_needed(ctl, pipeline)) { pipeline 37 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.h int mdp5_ctl_set_cursor(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline, pipeline 55 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.h int mdp5_ctl_blend(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline, pipeline 72 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.h u32 mdp5_ctl_commit(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline, pipeline 199 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c struct mdp5_pipeline *pipeline = mdp5_crtc_get_pipeline(encoder->crtc); pipeline 208 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c mdp5_ctl_set_encoder_state(ctl, pipeline, false); pipeline 213 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c mdp5_ctl_commit(ctl, pipeline, mdp_ctl_flush_mask_encoder(intf), true); pipeline 236 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c struct mdp5_pipeline *pipeline = mdp5_crtc_get_pipeline(encoder->crtc); pipeline 247 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c mdp5_ctl_commit(ctl, pipeline, mdp_ctl_flush_mask_encoder(intf), true); pipeline 249 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c mdp5_ctl_set_encoder_state(ctl, pipeline, true); pipeline 303 drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c mdp5_cstate->pipeline.intf = intf; pipeline 120 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h struct mdp5_pipeline pipeline; pipeline 506 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c struct mdp5_pipeline *pipeline = pipeline 516 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c mdp5_ctl_commit(ctl, pipeline, mdp5_plane_get_flush(plane), true); pipeline 358 drivers/gpu/drm/sun4i/sun4i_drv.c struct device_node *pipeline = of_parse_phandle(np, pipeline 361 drivers/gpu/drm/sun4i/sun4i_drv.c if (!pipeline) pipeline 364 drivers/gpu/drm/sun4i/sun4i_drv.c kfifo_put(&list.fifo, pipeline); pipeline 122 drivers/gpu/drm/xen/xen_drm_front.c int xen_drm_front_mode_set(struct xen_drm_front_drm_pipeline *pipeline, pipeline 132 drivers/gpu/drm/xen/xen_drm_front.c front_info = pipeline->drm_info->front_info; pipeline 133 drivers/gpu/drm/xen/xen_drm_front.c evtchnl = &front_info->evt_pairs[pipeline->index].req; pipeline 378 drivers/gpu/drm/xen/xen_drm_front.c xen_drm_front_kms_on_frame_done(&drm_info->pipeline[conn_idx], pipeline 129 drivers/gpu/drm/xen/xen_drm_front.h struct xen_drm_front_drm_pipeline pipeline[XEN_DRM_FRONT_MAX_CRTCS]; pipeline 142 drivers/gpu/drm/xen/xen_drm_front.h int xen_drm_front_mode_set(struct xen_drm_front_drm_pipeline *pipeline, pipeline 48 drivers/gpu/drm/xen/xen_drm_front_conn.c struct xen_drm_front_drm_pipeline *pipeline = pipeline 52 drivers/gpu/drm/xen/xen_drm_front_conn.c pipeline->conn_connected = false; pipeline 54 drivers/gpu/drm/xen/xen_drm_front_conn.c return pipeline->conn_connected ? connector_status_connected : pipeline 62 drivers/gpu/drm/xen/xen_drm_front_conn.c struct xen_drm_front_drm_pipeline *pipeline = pipeline 73 drivers/gpu/drm/xen/xen_drm_front_conn.c videomode.hactive = pipeline->width; pipeline 74 drivers/gpu/drm/xen/xen_drm_front_conn.c videomode.vactive = pipeline->height; pipeline 103 drivers/gpu/drm/xen/xen_drm_front_conn.c struct xen_drm_front_drm_pipeline *pipeline = pipeline 108 drivers/gpu/drm/xen/xen_drm_front_conn.c pipeline->conn_connected = true; pipeline 98 drivers/gpu/drm/xen/xen_drm_front_kms.c static void send_pending_event(struct xen_drm_front_drm_pipeline *pipeline) pipeline 100 drivers/gpu/drm/xen/xen_drm_front_kms.c struct drm_crtc *crtc = &pipeline->pipe.crtc; pipeline 105 drivers/gpu/drm/xen/xen_drm_front_kms.c if (pipeline->pending_event) pipeline 106 drivers/gpu/drm/xen/xen_drm_front_kms.c drm_crtc_send_vblank_event(crtc, pipeline->pending_event); pipeline 107 drivers/gpu/drm/xen/xen_drm_front_kms.c pipeline->pending_event = NULL; pipeline 115 drivers/gpu/drm/xen/xen_drm_front_kms.c struct xen_drm_front_drm_pipeline *pipeline = pipeline 124 drivers/gpu/drm/xen/xen_drm_front_kms.c ret = xen_drm_front_mode_set(pipeline, crtc->x, crtc->y, pipeline 131 drivers/gpu/drm/xen/xen_drm_front_kms.c pipeline->conn_connected = false; pipeline 139 drivers/gpu/drm/xen/xen_drm_front_kms.c struct xen_drm_front_drm_pipeline *pipeline = pipeline 144 drivers/gpu/drm/xen/xen_drm_front_kms.c ret = xen_drm_front_mode_set(pipeline, 0, 0, 0, 0, 0, pipeline 152 drivers/gpu/drm/xen/xen_drm_front_kms.c pipeline->conn_connected = true; pipeline 155 drivers/gpu/drm/xen/xen_drm_front_kms.c send_pending_event(pipeline); pipeline 158 drivers/gpu/drm/xen/xen_drm_front_kms.c void xen_drm_front_kms_on_frame_done(struct xen_drm_front_drm_pipeline *pipeline, pipeline 166 drivers/gpu/drm/xen/xen_drm_front_kms.c cancel_delayed_work(&pipeline->pflip_to_worker); pipeline 168 drivers/gpu/drm/xen/xen_drm_front_kms.c send_pending_event(pipeline); pipeline 174 drivers/gpu/drm/xen/xen_drm_front_kms.c struct xen_drm_front_drm_pipeline *pipeline = pipeline 180 drivers/gpu/drm/xen/xen_drm_front_kms.c send_pending_event(pipeline); pipeline 199 drivers/gpu/drm/xen/xen_drm_front_kms.c struct xen_drm_front_drm_pipeline *pipeline = pipeline 201 drivers/gpu/drm/xen/xen_drm_front_kms.c struct xen_drm_front_drm_info *drm_info = pipeline->drm_info; pipeline 204 drivers/gpu/drm/xen/xen_drm_front_kms.c schedule_delayed_work(&pipeline->pflip_to_worker, pipeline 208 drivers/gpu/drm/xen/xen_drm_front_kms.c pipeline->index, pipeline 213 drivers/gpu/drm/xen/xen_drm_front_kms.c pipeline->conn_connected = false; pipeline 233 drivers/gpu/drm/xen/xen_drm_front_kms.c struct xen_drm_front_drm_pipeline *pipeline = pipeline 244 drivers/gpu/drm/xen/xen_drm_front_kms.c WARN_ON(pipeline->pending_event); pipeline 249 drivers/gpu/drm/xen/xen_drm_front_kms.c pipeline->pending_event = event; pipeline 254 drivers/gpu/drm/xen/xen_drm_front_kms.c send_pending_event(pipeline); pipeline 267 drivers/gpu/drm/xen/xen_drm_front_kms.c send_pending_event(pipeline); pipeline 275 drivers/gpu/drm/xen/xen_drm_front_kms.c struct xen_drm_front_drm_pipeline *pipeline = pipeline 279 drivers/gpu/drm/xen/xen_drm_front_kms.c if (mode->hdisplay != pipeline->width) pipeline 282 drivers/gpu/drm/xen/xen_drm_front_kms.c if (mode->vdisplay != pipeline->height) pipeline 298 drivers/gpu/drm/xen/xen_drm_front_kms.c struct xen_drm_front_drm_pipeline *pipeline) pipeline 305 drivers/gpu/drm/xen/xen_drm_front_kms.c pipeline->drm_info = drm_info; pipeline 306 drivers/gpu/drm/xen/xen_drm_front_kms.c pipeline->index = index; pipeline 307 drivers/gpu/drm/xen/xen_drm_front_kms.c pipeline->height = cfg->height; pipeline 308 drivers/gpu/drm/xen/xen_drm_front_kms.c pipeline->width = cfg->width; pipeline 310 drivers/gpu/drm/xen/xen_drm_front_kms.c INIT_DELAYED_WORK(&pipeline->pflip_to_worker, pflip_to_worker); pipeline 312 drivers/gpu/drm/xen/xen_drm_front_kms.c ret = xen_drm_front_conn_init(drm_info, &pipeline->conn); pipeline 318 drivers/gpu/drm/xen/xen_drm_front_kms.c return drm_simple_display_pipe_init(dev, &pipeline->pipe, pipeline 321 drivers/gpu/drm/xen/xen_drm_front_kms.c &pipeline->conn); pipeline 340 drivers/gpu/drm/xen/xen_drm_front_kms.c struct xen_drm_front_drm_pipeline *pipeline = pipeline 341 drivers/gpu/drm/xen/xen_drm_front_kms.c &drm_info->pipeline[i]; pipeline 343 drivers/gpu/drm/xen/xen_drm_front_kms.c ret = display_pipe_init(drm_info, i, cfg, pipeline); pipeline 360 drivers/gpu/drm/xen/xen_drm_front_kms.c struct xen_drm_front_drm_pipeline *pipeline = pipeline 361 drivers/gpu/drm/xen/xen_drm_front_kms.c &drm_info->pipeline[i]; pipeline 363 drivers/gpu/drm/xen/xen_drm_front_kms.c cancel_delayed_work_sync(&pipeline->pflip_to_worker); pipeline 365 drivers/gpu/drm/xen/xen_drm_front_kms.c send_pending_event(pipeline); pipeline 23 drivers/gpu/drm/xen/xen_drm_front_kms.h void xen_drm_front_kms_on_frame_done(struct xen_drm_front_drm_pipeline *pipeline, pipeline 236 drivers/isdn/mISDN/dsp.h pipeline; pipeline 271 drivers/isdn/mISDN/dsp.h extern int dsp_pipeline_init(struct dsp_pipeline *pipeline); pipeline 272 drivers/isdn/mISDN/dsp.h extern void dsp_pipeline_destroy(struct dsp_pipeline *pipeline); pipeline 273 drivers/isdn/mISDN/dsp.h extern int dsp_pipeline_build(struct dsp_pipeline *pipeline, const char *cfg); pipeline 274 drivers/isdn/mISDN/dsp.h extern void dsp_pipeline_process_tx(struct dsp_pipeline *pipeline, u8 *data, pipeline 276 drivers/isdn/mISDN/dsp.h extern void dsp_pipeline_process_rx(struct dsp_pipeline *pipeline, u8 *data, pipeline 612 drivers/isdn/mISDN/dsp_cmx.c if (member->dsp->pipeline.inuse) { pipeline 1610 drivers/isdn/mISDN/dsp_cmx.c if (dsp->pipeline.inuse) pipeline 1611 drivers/isdn/mISDN/dsp_cmx.c dsp_pipeline_process_tx(&dsp->pipeline, nskb->data, pipeline 562 drivers/isdn/mISDN/dsp_core.c dsp->pipeline.inuse = 1; pipeline 564 drivers/isdn/mISDN/dsp_core.c ret = dsp_pipeline_build(&dsp->pipeline, pipeline 718 drivers/isdn/mISDN/dsp_core.c if (dsp->pipeline.inuse) pipeline 719 drivers/isdn/mISDN/dsp_core.c dsp_pipeline_process_rx(&dsp->pipeline, skb->data, pipeline 986 drivers/isdn/mISDN/dsp_core.c dsp_pipeline_destroy(&dsp->pipeline); pipeline 1101 drivers/isdn/mISDN/dsp_core.c dsp_pipeline_init(&ndsp->pipeline); pipeline 84 drivers/isdn/mISDN/dsp_dtmf.c if (dsp->pipeline.inuse) { pipeline 177 drivers/isdn/mISDN/dsp_pipeline.c int dsp_pipeline_init(struct dsp_pipeline *pipeline) pipeline 179 drivers/isdn/mISDN/dsp_pipeline.c if (!pipeline) pipeline 182 drivers/isdn/mISDN/dsp_pipeline.c INIT_LIST_HEAD(&pipeline->list); pipeline 191 drivers/isdn/mISDN/dsp_pipeline.c static inline void _dsp_pipeline_destroy(struct dsp_pipeline *pipeline) pipeline 195 drivers/isdn/mISDN/dsp_pipeline.c list_for_each_entry_safe(entry, n, &pipeline->list, list) { pipeline 198 drivers/isdn/mISDN/dsp_pipeline.c dsp_hwec_disable(container_of(pipeline, struct dsp, pipeline 199 drivers/isdn/mISDN/dsp_pipeline.c pipeline)); pipeline 206 drivers/isdn/mISDN/dsp_pipeline.c void dsp_pipeline_destroy(struct dsp_pipeline *pipeline) pipeline 209 drivers/isdn/mISDN/dsp_pipeline.c if (!pipeline) pipeline 212 drivers/isdn/mISDN/dsp_pipeline.c _dsp_pipeline_destroy(pipeline); pipeline 219 drivers/isdn/mISDN/dsp_pipeline.c int dsp_pipeline_build(struct dsp_pipeline *pipeline, const char *cfg) pipeline 227 drivers/isdn/mISDN/dsp_pipeline.c if (!pipeline) pipeline 230 drivers/isdn/mISDN/dsp_pipeline.c if (!list_empty(&pipeline->list)) pipeline 231 drivers/isdn/mISDN/dsp_pipeline.c _dsp_pipeline_destroy(pipeline); pipeline 262 drivers/isdn/mISDN/dsp_pipeline.c dsp_hwec_enable(container_of(pipeline, pipeline 263 drivers/isdn/mISDN/dsp_pipeline.c struct dsp, pipeline), args); pipeline 265 drivers/isdn/mISDN/dsp_pipeline.c &pipeline->list); pipeline 270 drivers/isdn/mISDN/dsp_pipeline.c list, &pipeline->list); pipeline 301 drivers/isdn/mISDN/dsp_pipeline.c if (!list_empty(&pipeline->list)) pipeline 302 drivers/isdn/mISDN/dsp_pipeline.c pipeline->inuse = 1; pipeline 304 drivers/isdn/mISDN/dsp_pipeline.c pipeline->inuse = 0; pipeline 314 drivers/isdn/mISDN/dsp_pipeline.c void dsp_pipeline_process_tx(struct dsp_pipeline *pipeline, u8 *data, int len) pipeline 318 drivers/isdn/mISDN/dsp_pipeline.c if (!pipeline) pipeline 321 drivers/isdn/mISDN/dsp_pipeline.c list_for_each_entry(entry, &pipeline->list, list) pipeline 326 drivers/isdn/mISDN/dsp_pipeline.c void dsp_pipeline_process_rx(struct dsp_pipeline *pipeline, u8 *data, int len, pipeline 331 drivers/isdn/mISDN/dsp_pipeline.c if (!pipeline) pipeline 334 drivers/isdn/mISDN/dsp_pipeline.c list_for_each_entry_reverse(entry, &pipeline->list, list) pipeline 633 drivers/media/platform/atmel/atmel-isc-base.c static void isc_set_pipeline(struct isc_device *isc, u32 pipeline) pipeline 643 drivers/media/platform/atmel/atmel-isc-base.c val = pipeline & BIT(i) ? 1 : 0; pipeline 644 drivers/media/platform/atmel/atmel-isc-base.c regmap_field_write(isc->pipeline[i], val); pipeline 647 drivers/media/platform/atmel/atmel-isc-base.c if (!pipeline) pipeline 728 drivers/media/platform/atmel/atmel-isc-base.c u32 pfe_cfg0, rlp_mode, dcfg, mask, pipeline; pipeline 733 drivers/media/platform/atmel/atmel-isc-base.c pipeline = isc->config.bits_pipeline; pipeline 752 drivers/media/platform/atmel/atmel-isc-base.c isc_set_pipeline(isc, pipeline); pipeline 2149 drivers/media/platform/atmel/atmel-isc-base.c isc->pipeline[i] = regs; pipeline 222 drivers/media/platform/atmel/atmel-isc.h struct regmap_field *pipeline[ISC_PIPE_LINE_NODE_NUM]; pipeline 175 drivers/media/platform/stm32/stm32-dcmi.c struct media_pipeline pipeline; pipeline 739 drivers/media/platform/stm32/stm32-dcmi.c ret = media_pipeline_start(&dcmi->vdev->entity, &dcmi->pipeline); pipeline 277 drivers/net/wireless/ti/wl18xx/acx.h struct wl18xx_acx_pipeline_stats pipeline; pipeline 143 drivers/net/wireless/ti/wl18xx/debugfs.c WL18XX_DEBUGFS_FWSTATS_FILE(pipeline, hs_tx_stat_fifo_int, "%u"); pipeline 144 drivers/net/wireless/ti/wl18xx/debugfs.c WL18XX_DEBUGFS_FWSTATS_FILE(pipeline, enc_tx_stat_fifo_int, "%u"); pipeline 145 drivers/net/wireless/ti/wl18xx/debugfs.c WL18XX_DEBUGFS_FWSTATS_FILE(pipeline, enc_rx_stat_fifo_int, "%u"); pipeline 146 drivers/net/wireless/ti/wl18xx/debugfs.c WL18XX_DEBUGFS_FWSTATS_FILE(pipeline, rx_complete_stat_fifo_int, "%u"); pipeline 147 drivers/net/wireless/ti/wl18xx/debugfs.c WL18XX_DEBUGFS_FWSTATS_FILE(pipeline, pre_proc_swi, "%u"); pipeline 148 drivers/net/wireless/ti/wl18xx/debugfs.c WL18XX_DEBUGFS_FWSTATS_FILE(pipeline, post_proc_swi, "%u"); pipeline 149 drivers/net/wireless/ti/wl18xx/debugfs.c WL18XX_DEBUGFS_FWSTATS_FILE(pipeline, sec_frag_swi, "%u"); pipeline 150 drivers/net/wireless/ti/wl18xx/debugfs.c WL18XX_DEBUGFS_FWSTATS_FILE(pipeline, pre_to_defrag_swi, "%u"); pipeline 151 drivers/net/wireless/ti/wl18xx/debugfs.c WL18XX_DEBUGFS_FWSTATS_FILE(pipeline, defrag_to_rx_xfer_swi, "%u"); pipeline 152 drivers/net/wireless/ti/wl18xx/debugfs.c WL18XX_DEBUGFS_FWSTATS_FILE(pipeline, dec_packet_in, "%u"); pipeline 153 drivers/net/wireless/ti/wl18xx/debugfs.c WL18XX_DEBUGFS_FWSTATS_FILE(pipeline, dec_packet_in_fifo_full, "%u"); pipeline 154 drivers/net/wireless/ti/wl18xx/debugfs.c WL18XX_DEBUGFS_FWSTATS_FILE(pipeline, dec_packet_out, "%u"); pipeline 156 drivers/net/wireless/ti/wl18xx/debugfs.c WL18XX_DEBUGFS_FWSTATS_FILE_ARRAY(pipeline, pipeline_fifo_full, pipeline 529 drivers/net/wireless/ti/wl18xx/debugfs.c DEBUGFS_FWSTATS_ADD(pipeline, hs_tx_stat_fifo_int); pipeline 530 drivers/net/wireless/ti/wl18xx/debugfs.c DEBUGFS_FWSTATS_ADD(pipeline, enc_tx_stat_fifo_int); pipeline 531 drivers/net/wireless/ti/wl18xx/debugfs.c DEBUGFS_FWSTATS_ADD(pipeline, enc_rx_stat_fifo_int); pipeline 532 drivers/net/wireless/ti/wl18xx/debugfs.c DEBUGFS_FWSTATS_ADD(pipeline, rx_complete_stat_fifo_int); pipeline 533 drivers/net/wireless/ti/wl18xx/debugfs.c DEBUGFS_FWSTATS_ADD(pipeline, pre_proc_swi); pipeline 534 drivers/net/wireless/ti/wl18xx/debugfs.c DEBUGFS_FWSTATS_ADD(pipeline, post_proc_swi); pipeline 535 drivers/net/wireless/ti/wl18xx/debugfs.c DEBUGFS_FWSTATS_ADD(pipeline, sec_frag_swi); pipeline 536 drivers/net/wireless/ti/wl18xx/debugfs.c DEBUGFS_FWSTATS_ADD(pipeline, pre_to_defrag_swi); pipeline 537 drivers/net/wireless/ti/wl18xx/debugfs.c DEBUGFS_FWSTATS_ADD(pipeline, defrag_to_rx_xfer_swi); pipeline 538 drivers/net/wireless/ti/wl18xx/debugfs.c DEBUGFS_FWSTATS_ADD(pipeline, dec_packet_in); pipeline 539 drivers/net/wireless/ti/wl18xx/debugfs.c DEBUGFS_FWSTATS_ADD(pipeline, dec_packet_in_fifo_full); pipeline 540 drivers/net/wireless/ti/wl18xx/debugfs.c DEBUGFS_FWSTATS_ADD(pipeline, dec_packet_out); pipeline 541 drivers/net/wireless/ti/wl18xx/debugfs.c DEBUGFS_FWSTATS_ADD(pipeline, pipeline_fifo_full); pipeline 1640 drivers/staging/media/ipu3/ipu3-abi.h struct imgu_abi_binary_pipeline_info pipeline; pipeline 24 drivers/staging/media/ipu3/ipu3-css-fw.c bi->info.isp.sp.id, bi->info.isp.sp.pipeline.mode, pipeline 191 drivers/staging/media/ipu3/ipu3-css-fw.c if (bi->info.isp.sp.pipeline.mode >= IPU3_CSS_PIPE_ID_NUM) pipeline 1026 drivers/staging/media/ipu3/ipu3-css.c bi->info.isp.sp.pipeline.isp_pipe_version; pipeline 1649 drivers/staging/media/ipu3/ipu3-css.c if (bi->info.isp.sp.pipeline.mode != binary_mode) pipeline 484 drivers/staging/media/ipu3/ipu3-v4l2.c r = media_pipeline_start(&node->vdev.entity, &imgu_pipe->pipeline); pipeline 115 drivers/staging/media/ipu3/ipu3.h struct media_pipeline pipeline; pipeline 66 sound/soc/sof/pm.c struct sof_ipc_pipe_new *pipeline; pipeline 98 sound/soc/sof/pm.c pipeline = swidget->private; pipeline 99 sound/soc/sof/pm.c ret = sof_load_pipeline_ipc(sdev, pipeline, &r); pipeline 561 sound/soc/sof/sof-priv.h struct sof_ipc_pipe_new *pipeline, pipeline 1364 sound/soc/sof/topology.c struct sof_ipc_pipe_new *pipeline, pipeline 1370 sound/soc/sof/topology.c ret = sof_ipc_tx_message(sdev->ipc, pipeline->hdr.cmd, pipeline, pipeline 1371 sound/soc/sof/topology.c sizeof(*pipeline), r, sizeof(*r)); pipeline 1378 sound/soc/sof/topology.c ret = snd_sof_dsp_core_power_up(sdev, 1 << pipeline->core); pipeline 1381 sound/soc/sof/topology.c pipeline->core); pipeline 1386 sound/soc/sof/topology.c sdev->enabled_cores_mask |= 1 << pipeline->core; pipeline 1416 sound/soc/sof/topology.c struct sof_ipc_pipe_new *pipeline; pipeline 1420 sound/soc/sof/topology.c pipeline = kzalloc(sizeof(*pipeline), GFP_KERNEL); pipeline 1421 sound/soc/sof/topology.c if (!pipeline) pipeline 1425 sound/soc/sof/topology.c pipeline->hdr.size = sizeof(*pipeline); pipeline 1426 sound/soc/sof/topology.c pipeline->hdr.cmd = SOF_IPC_GLB_TPLG_MSG | SOF_IPC_TPLG_PIPE_NEW; pipeline 1427 sound/soc/sof/topology.c pipeline->pipeline_id = index; pipeline 1428 sound/soc/sof/topology.c pipeline->comp_id = swidget->comp_id; pipeline 1439 sound/soc/sof/topology.c pipeline->sched_id = comp_swidget->comp_id; pipeline 1442 sound/soc/sof/topology.c pipeline->pipeline_id, pipeline->comp_id, pipeline->sched_id); pipeline 1444 sound/soc/sof/topology.c ret = sof_parse_tokens(scomp, pipeline, sched_tokens, pipeline 1454 sound/soc/sof/topology.c swidget->widget->name, pipeline->period, pipeline->priority, pipeline 1455 sound/soc/sof/topology.c pipeline->period_mips, pipeline->core, pipeline->frames_per_sched); pipeline 1457 sound/soc/sof/topology.c swidget->private = pipeline; pipeline 1460 sound/soc/sof/topology.c ret = sof_load_pipeline_ipc(sdev, pipeline, r); pipeline 1464 sound/soc/sof/topology.c kfree(pipeline); pipeline 2184 sound/soc/sof/topology.c struct sof_ipc_pipe_new *pipeline; pipeline 2214 sound/soc/sof/topology.c pipeline = swidget->private; pipeline 2215 sound/soc/sof/topology.c ret = snd_sof_dsp_core_power_down(sdev, 1 << pipeline->core); pipeline 2218 sound/soc/sof/topology.c pipeline->core); pipeline 2221 sound/soc/sof/topology.c sdev->enabled_cores_mask &= ~(1 << pipeline->core); pipeline 33 tools/testing/selftests/kvm/lib/assert.c const char *pipeline = "|cat -n 1>&2"; pipeline 34 tools/testing/selftests/kvm/lib/assert.c char cmd[strlen(addr2line) + strlen(pipeline) + pipeline 51 tools/testing/selftests/kvm/lib/assert.c c += sprintf(c, "%s", pipeline);