pipe_vig          539 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h 		case SSPP_VIG0: return (mdp5_cfg->pipe_vig.base[0]);
pipe_vig          540 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h 		case SSPP_VIG1: return (mdp5_cfg->pipe_vig.base[1]);
pipe_vig          541 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h 		case SSPP_VIG2: return (mdp5_cfg->pipe_vig.base[2]);
pipe_vig          547 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h 		case SSPP_VIG3: return (mdp5_cfg->pipe_vig.base[3]);
pipe_vig           38 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 	.pipe_vig = {
pipe_vig          122 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 	.pipe_vig = {
pipe_vig          212 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 	.pipe_vig = {
pipe_vig          299 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 	.pipe_vig = {
pipe_vig          374 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 	.pipe_vig = {
pipe_vig          454 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 	.pipe_vig = {
pipe_vig          559 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 	.pipe_vig = {
pipe_vig          647 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c 	.pipe_vig = {
pipe_vig           85 drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.h 	struct mdp5_pipe_block pipe_vig;
pipe_vig          851 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c 	ret = construct_pipes(mdp5_kms, hw_cfg->pipe_vig.count, vig_planes,
pipe_vig          852 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c 			hw_cfg->pipe_vig.base, hw_cfg->pipe_vig.caps);