pipe_stats       1717 drivers/gpu/drm/i915/i915_irq.c 				  u32 iir, u32 pipe_stats[I915_MAX_PIPES])
pipe_stats       1761 drivers/gpu/drm/i915/i915_irq.c 		pipe_stats[pipe] = I915_READ(reg) & status_mask;
pipe_stats       1773 drivers/gpu/drm/i915/i915_irq.c 		if (pipe_stats[pipe]) {
pipe_stats       1774 drivers/gpu/drm/i915/i915_irq.c 			I915_WRITE(reg, pipe_stats[pipe]);
pipe_stats       1782 drivers/gpu/drm/i915/i915_irq.c 				      u16 iir, u32 pipe_stats[I915_MAX_PIPES])
pipe_stats       1787 drivers/gpu/drm/i915/i915_irq.c 		if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
pipe_stats       1790 drivers/gpu/drm/i915/i915_irq.c 		if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
pipe_stats       1793 drivers/gpu/drm/i915/i915_irq.c 		if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
pipe_stats       1799 drivers/gpu/drm/i915/i915_irq.c 				      u32 iir, u32 pipe_stats[I915_MAX_PIPES])
pipe_stats       1805 drivers/gpu/drm/i915/i915_irq.c 		if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
pipe_stats       1808 drivers/gpu/drm/i915/i915_irq.c 		if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
pipe_stats       1811 drivers/gpu/drm/i915/i915_irq.c 		if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
pipe_stats       1814 drivers/gpu/drm/i915/i915_irq.c 		if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
pipe_stats       1823 drivers/gpu/drm/i915/i915_irq.c 				      u32 iir, u32 pipe_stats[I915_MAX_PIPES])
pipe_stats       1829 drivers/gpu/drm/i915/i915_irq.c 		if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
pipe_stats       1832 drivers/gpu/drm/i915/i915_irq.c 		if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
pipe_stats       1835 drivers/gpu/drm/i915/i915_irq.c 		if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
pipe_stats       1838 drivers/gpu/drm/i915/i915_irq.c 		if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
pipe_stats       1845 drivers/gpu/drm/i915/i915_irq.c 	if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
pipe_stats       1850 drivers/gpu/drm/i915/i915_irq.c 					    u32 pipe_stats[I915_MAX_PIPES])
pipe_stats       1855 drivers/gpu/drm/i915/i915_irq.c 		if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
pipe_stats       1858 drivers/gpu/drm/i915/i915_irq.c 		if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
pipe_stats       1861 drivers/gpu/drm/i915/i915_irq.c 		if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
pipe_stats       1865 drivers/gpu/drm/i915/i915_irq.c 	if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
pipe_stats       1953 drivers/gpu/drm/i915/i915_irq.c 		u32 pipe_stats[I915_MAX_PIPES] = {};
pipe_stats       1993 drivers/gpu/drm/i915/i915_irq.c 		i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
pipe_stats       2017 drivers/gpu/drm/i915/i915_irq.c 		valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
pipe_stats       2038 drivers/gpu/drm/i915/i915_irq.c 		u32 pipe_stats[I915_MAX_PIPES] = {};
pipe_stats       2075 drivers/gpu/drm/i915/i915_irq.c 		i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
pipe_stats       2097 drivers/gpu/drm/i915/i915_irq.c 		valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
pipe_stats       4024 drivers/gpu/drm/i915/i915_irq.c 		u32 pipe_stats[I915_MAX_PIPES] = {};
pipe_stats       4036 drivers/gpu/drm/i915/i915_irq.c 		i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
pipe_stats       4049 drivers/gpu/drm/i915/i915_irq.c 		i8xx_pipestat_irq_handler(dev_priv, iir, pipe_stats);
pipe_stats       4124 drivers/gpu/drm/i915/i915_irq.c 		u32 pipe_stats[I915_MAX_PIPES] = {};
pipe_stats       4141 drivers/gpu/drm/i915/i915_irq.c 		i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
pipe_stats       4157 drivers/gpu/drm/i915/i915_irq.c 		i915_pipestat_irq_handler(dev_priv, iir, pipe_stats);
pipe_stats       4267 drivers/gpu/drm/i915/i915_irq.c 		u32 pipe_stats[I915_MAX_PIPES] = {};
pipe_stats       4283 drivers/gpu/drm/i915/i915_irq.c 		i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
pipe_stats       4302 drivers/gpu/drm/i915/i915_irq.c 		i965_pipestat_irq_handler(dev_priv, iir, pipe_stats);