pipe_src_param     41 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 		const display_pipe_source_params_st pipe_src_param);
pipe_src_param    236 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 		const display_pipe_source_params_st pipe_src_param)
pipe_src_param    245 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 	bool surf_linear = (pipe_src_param.sw_mode == dm_sw_linear);
pipe_src_param    246 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 	bool surf_vert = (pipe_src_param.source_scan == dm_vert);
pipe_src_param    670 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 		const display_pipe_source_params_st pipe_src_param,
pipe_src_param    682 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 		vp_width = pipe_src_param.viewport_width_c / ppe;
pipe_src_param    683 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 		vp_height = pipe_src_param.viewport_height_c;
pipe_src_param    684 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 		data_pitch = pipe_src_param.data_pitch_c;
pipe_src_param    685 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 		meta_pitch = pipe_src_param.meta_pitch_c;
pipe_src_param    687 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 		vp_width = pipe_src_param.viewport_width / ppe;
pipe_src_param    688 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 		vp_height = pipe_src_param.viewport_height;
pipe_src_param    689 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 		data_pitch = pipe_src_param.data_pitch;
pipe_src_param    690 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 		meta_pitch = pipe_src_param.meta_pitch;
pipe_src_param    713 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 			pipe_src_param.source_format,
pipe_src_param    714 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 			pipe_src_param.sw_mode,
pipe_src_param    715 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 			pipe_src_param.macro_tile_size,
pipe_src_param    716 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 			pipe_src_param.source_scan,
pipe_src_param    722 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 		const display_pipe_source_params_st pipe_src_param)
pipe_src_param    725 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 	rq_param->yuv420 = pipe_src_param.source_format == dm_420_8
pipe_src_param    726 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 			|| pipe_src_param.source_format == dm_420_10;
pipe_src_param    727 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 	rq_param->yuv420_10bpc = pipe_src_param.source_format == dm_420_10;
pipe_src_param    733 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 			pipe_src_param,
pipe_src_param    736 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 	if (is_dual_plane((enum source_format_class)(pipe_src_param.source_format))) {
pipe_src_param    742 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 				pipe_src_param,
pipe_src_param    747 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 	handle_det_buf_split(mode_lib, rq_param, pipe_src_param);
pipe_src_param     41 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 		const display_pipe_source_params_st pipe_src_param);
pipe_src_param    236 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 		const display_pipe_source_params_st pipe_src_param)
pipe_src_param    245 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 	bool surf_linear = (pipe_src_param.sw_mode == dm_sw_linear);
pipe_src_param    246 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 	bool surf_vert = (pipe_src_param.source_scan == dm_vert);
pipe_src_param    670 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 		const display_pipe_source_params_st pipe_src_param,
pipe_src_param    682 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 		vp_width = pipe_src_param.viewport_width_c / ppe;
pipe_src_param    683 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 		vp_height = pipe_src_param.viewport_height_c;
pipe_src_param    684 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 		data_pitch = pipe_src_param.data_pitch_c;
pipe_src_param    685 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 		meta_pitch = pipe_src_param.meta_pitch_c;
pipe_src_param    687 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 		vp_width = pipe_src_param.viewport_width / ppe;
pipe_src_param    688 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 		vp_height = pipe_src_param.viewport_height;
pipe_src_param    689 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 		data_pitch = pipe_src_param.data_pitch;
pipe_src_param    690 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 		meta_pitch = pipe_src_param.meta_pitch;
pipe_src_param    713 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 			pipe_src_param.source_format,
pipe_src_param    714 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 			pipe_src_param.sw_mode,
pipe_src_param    715 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 			pipe_src_param.macro_tile_size,
pipe_src_param    716 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 			pipe_src_param.source_scan,
pipe_src_param    722 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 		const display_pipe_source_params_st pipe_src_param)
pipe_src_param    725 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 	rq_param->yuv420 = pipe_src_param.source_format == dm_420_8
pipe_src_param    726 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 			|| pipe_src_param.source_format == dm_420_10;
pipe_src_param    727 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 	rq_param->yuv420_10bpc = pipe_src_param.source_format == dm_420_10;
pipe_src_param    733 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 			pipe_src_param,
pipe_src_param    736 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 	if (is_dual_plane((enum source_format_class)(pipe_src_param.source_format))) {
pipe_src_param    742 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 				pipe_src_param,
pipe_src_param    747 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 	handle_det_buf_split(mode_lib, rq_param, pipe_src_param);
pipe_src_param    219 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 		const display_pipe_source_params_st pipe_src_param)
pipe_src_param    228 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 	bool surf_linear = (pipe_src_param.sw_mode == dm_sw_linear);
pipe_src_param    229 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 	bool surf_vert = (pipe_src_param.source_scan == dm_vert);
pipe_src_param    275 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 		const struct _vcs_dpi_display_pipe_source_params_st pipe_src_param)
pipe_src_param    284 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 	bool surf_linear = (pipe_src_param.sw_mode == dm_sw_linear);
pipe_src_param    285 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 	bool surf_vert = (pipe_src_param.source_scan == dm_vert);
pipe_src_param    541 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 		const struct _vcs_dpi_display_pipe_source_params_st pipe_src_param,
pipe_src_param    607 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 		vp_width = pipe_src_param.viewport_width_c / ppe;
pipe_src_param    608 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 		vp_height = pipe_src_param.viewport_height_c;
pipe_src_param    609 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 		data_pitch = pipe_src_param.data_pitch_c;
pipe_src_param    610 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 		meta_pitch = pipe_src_param.meta_pitch_c;
pipe_src_param    612 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 		vp_width = pipe_src_param.viewport_width / ppe;
pipe_src_param    613 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 		vp_height = pipe_src_param.viewport_height;
pipe_src_param    614 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 		data_pitch = pipe_src_param.data_pitch;
pipe_src_param    615 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 		meta_pitch = pipe_src_param.meta_pitch;
pipe_src_param    630 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 	surf_linear = (pipe_src_param.sw_mode == dm_sw_linear);
pipe_src_param    631 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 	surf_vert = (pipe_src_param.source_scan == dm_vert);
pipe_src_param    634 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 			(enum source_format_class) pipe_src_param.source_format,
pipe_src_param    656 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 							(enum source_macro_tile_size) pipe_src_param.macro_tile_size);
pipe_src_param    667 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 	if (pipe_src_param.sw_mode != dm_sw_linear)
pipe_src_param    915 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 			pipe_src_param.source_format,
pipe_src_param    916 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 			pipe_src_param.sw_mode,
pipe_src_param    917 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 			pipe_src_param.macro_tile_size,
pipe_src_param    918 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 			pipe_src_param.source_scan,
pipe_src_param    945 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 		const struct _vcs_dpi_display_pipe_source_params_st pipe_src_param)
pipe_src_param    948 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 	rq_param->yuv420 = pipe_src_param.source_format == dm_420_8
pipe_src_param    949 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 			|| pipe_src_param.source_format == dm_420_10;
pipe_src_param    950 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 	rq_param->yuv420_10bpc = pipe_src_param.source_format == dm_420_10;
pipe_src_param    957 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 			pipe_src_param,
pipe_src_param    960 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 	if (is_dual_plane((enum source_format_class) pipe_src_param.source_format)) {
pipe_src_param    967 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 				pipe_src_param,
pipe_src_param    972 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 	handle_det_buf_split(mode_lib, rq_param, pipe_src_param);
pipe_src_param     50 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.h 		const struct _vcs_dpi_display_pipe_source_params_st pipe_src_param);