pipe_sblk 103 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c const struct dpu_sspp_sub_blks *pipe_sblk; pipe_sblk 151 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c fixed_buff_size = pdpu->pipe_sblk->common->pixel_ram_size; pipe_sblk 331 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c pdpu->pipe_qos_cfg.creq_vblank = pdpu->pipe_sblk->creq_vblank; pipe_sblk 333 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c pdpu->pipe_sblk->danger_vblank; pipe_sblk 699 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c width_threshold = dpu_plane[i]->pipe_sblk->common->maxlinewidth; pipe_sblk 856 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c min_scale = FRAC_16_16(1, pdpu->pipe_sblk->maxdwnscale); pipe_sblk 858 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c pdpu->pipe_sblk->maxupscale << 16, pipe_sblk 877 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c max_linewidth = pdpu->pipe_sblk->common->maxlinewidth; pipe_sblk 1501 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c pdpu->pipe_sblk = pdpu->pipe_hw->cap->sblk; pipe_sblk 1502 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c if (!pdpu->pipe_sblk) { pipe_sblk 1508 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c format_list = pdpu->pipe_sblk->virt_format_list; pipe_sblk 1509 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c num_formats = pdpu->pipe_sblk->virt_num_formats; pipe_sblk 1512 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c format_list = pdpu->pipe_sblk->format_list; pipe_sblk 1513 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c num_formats = pdpu->pipe_sblk->num_formats;