pipe_param        753 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 		const display_pipe_params_st pipe_param)
pipe_param        758 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 	dml20_rq_dlg_get_rq_params(mode_lib, &rq_param, pipe_param.src);
pipe_param         47 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.h 		const display_pipe_params_st pipe_param);
pipe_param        753 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 		const display_pipe_params_st pipe_param)
pipe_param        758 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 	dml20v2_rq_dlg_get_rq_params(mode_lib, &rq_param, pipe_param.src);
pipe_param         47 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.h 		const display_pipe_params_st pipe_param);
pipe_param        680 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 		const display_pipe_params_st pipe_param,
pipe_param        692 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 		vp_width = pipe_param.src.viewport_width_c / ppe;
pipe_param        693 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 		vp_height = pipe_param.src.viewport_height_c;
pipe_param        694 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 		data_pitch = pipe_param.src.data_pitch_c;
pipe_param        695 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 		meta_pitch = pipe_param.src.meta_pitch_c;
pipe_param        697 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 		vp_width = pipe_param.src.viewport_width / ppe;
pipe_param        698 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 		vp_height = pipe_param.src.viewport_height;
pipe_param        699 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 		data_pitch = pipe_param.src.data_pitch;
pipe_param        700 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 		meta_pitch = pipe_param.src.meta_pitch;
pipe_param        703 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 	if (pipe_param.dest.odm_combine) {
pipe_param        708 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 		access_dir = (pipe_param.src.source_scan == dm_vert); // vp access direction: horizontal or vertical accessed
pipe_param        709 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 		hactive_half  = pipe_param.dest.hactive / 2;
pipe_param        711 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 			full_src_vp_width = pipe_param.scale_ratio_depth.hscl_ratio_c * pipe_param.dest.full_recout_width;
pipe_param        712 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 			src_hactive_half  = pipe_param.scale_ratio_depth.hscl_ratio_c * hactive_half;
pipe_param        714 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 			full_src_vp_width = pipe_param.scale_ratio_depth.hscl_ratio * pipe_param.dest.full_recout_width;
pipe_param        715 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 			src_hactive_half  = pipe_param.scale_ratio_depth.hscl_ratio * hactive_half;
pipe_param        740 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 	if (pipe_param.src.hostvm)
pipe_param        754 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 			pipe_param.src.source_format,
pipe_param        755 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 			pipe_param.src.sw_mode,
pipe_param        756 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 			pipe_param.src.macro_tile_size,
pipe_param        757 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 			pipe_param.src.source_scan,
pipe_param        758 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 			pipe_param.src.hostvm,
pipe_param        765 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 		const display_pipe_params_st pipe_param)
pipe_param        768 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 	rq_param->yuv420 = pipe_param.src.source_format == dm_420_8
pipe_param        769 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 			|| pipe_param.src.source_format == dm_420_10;
pipe_param        770 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 	rq_param->yuv420_10bpc = pipe_param.src.source_format == dm_420_10;
pipe_param        777 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 			pipe_param,
pipe_param        780 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 	if (is_dual_plane((enum source_format_class) (pipe_param.src.source_format))) {
pipe_param        787 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 				pipe_param,
pipe_param        792 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 	handle_det_buf_split(mode_lib, rq_param, pipe_param.src);
pipe_param        799 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 		const display_pipe_params_st pipe_param)
pipe_param        804 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 	dml_rq_dlg_get_rq_params(mode_lib, &rq_param, pipe_param);
pipe_param         47 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.h 		const display_pipe_params_st pipe_param);
pipe_param         64 drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h 		const display_pipe_params_st pipe_param);