pipe_offset 593 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c u32 pipe_offset = amdgpu_crtc->crtc_id; pipe_offset 626 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); pipe_offset 628 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp); pipe_offset 631 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); pipe_offset 619 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c u32 pipe_offset = amdgpu_crtc->crtc_id; pipe_offset 652 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); pipe_offset 654 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp); pipe_offset 657 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); pipe_offset 990 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8; pipe_offset 1020 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, pipe_offset 1023 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset) & pipe_offset 530 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8; pipe_offset 563 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, pipe_offset 566 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset) & pipe_offset 75 drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c int pipe_offset = mec * dqm->dev->shared_resources.num_pipe_per_mec pipe_offset 80 drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c if (test_bit(pipe_offset + i, pipe_offset 874 drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c int pipe_offset = pipe * get_queues_per_pipe(dqm); pipe_offset 877 drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c if (test_bit(pipe_offset + queue, pipe_offset 1903 drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c int pipe_offset = pipe * get_queues_per_pipe(dqm); pipe_offset 1906 drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c if (!test_bit(pipe_offset + queue, pipe_offset 212 drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c uint8_t pipe_offset = dal_irq_src - IRQ_TYPE_VBLANK; pipe_offset 215 drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c core_dc->current_state->res_ctx.pipe_ctx[pipe_offset].stream_res.tg; pipe_offset 8826 drivers/gpu/drm/radeon/cik.c u32 pipe_offset = radeon_crtc->crtc_id * 0x20; pipe_offset 8858 drivers/gpu/drm/radeon/cik.c WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset, pipe_offset 8861 drivers/gpu/drm/radeon/cik.c if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) & pipe_offset 1829 drivers/gpu/drm/radeon/evergreen.c u32 pipe_offset = radeon_crtc->crtc_id * 0x20; pipe_offset 1870 drivers/gpu/drm/radeon/evergreen.c WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset, pipe_offset 1873 drivers/gpu/drm/radeon/evergreen.c if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) & pipe_offset 2165 drivers/gpu/drm/radeon/evergreen.c u32 pipe_offset = radeon_crtc->crtc_id * 16; pipe_offset 2284 drivers/gpu/drm/radeon/evergreen.c arb_control3 = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset); pipe_offset 2288 drivers/gpu/drm/radeon/evergreen.c WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp); pipe_offset 2289 drivers/gpu/drm/radeon/evergreen.c WREG32(PIPE0_LATENCY_CONTROL + pipe_offset, pipe_offset 2293 drivers/gpu/drm/radeon/evergreen.c tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset); pipe_offset 2296 drivers/gpu/drm/radeon/evergreen.c WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp); pipe_offset 2297 drivers/gpu/drm/radeon/evergreen.c WREG32(PIPE0_LATENCY_CONTROL + pipe_offset, pipe_offset 2301 drivers/gpu/drm/radeon/evergreen.c WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, arb_control3); pipe_offset 1977 drivers/gpu/drm/radeon/si.c u32 pipe_offset = radeon_crtc->crtc_id * 0x20; pipe_offset 2007 drivers/gpu/drm/radeon/si.c WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset, pipe_offset 2010 drivers/gpu/drm/radeon/si.c if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &