pipe_idx_unsplit 2740 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	int i, j, pipe_idx, pipe_idx_unsplit;
pipe_idx_unsplit 2762 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	for (i = 0, pipe_idx = 0, pipe_idx_unsplit = 0; i < dc->res_pool->pipe_count; i++) {
pipe_idx_unsplit 2767 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			display_pipe_source_params_st *src = &pipes[pipe_idx_unsplit].pipe.src;
pipe_idx_unsplit 2768 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			display_pipe_dest_params_st *dst = &pipes[pipe_idx_unsplit].pipe.dest;
pipe_idx_unsplit 2770 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			dst->vstartup_start = context->bw_ctx.dml.vba.VStartup[pipe_idx_unsplit];
pipe_idx_unsplit 2771 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			dst->vupdate_offset = context->bw_ctx.dml.vba.VUpdateOffsetPix[pipe_idx_unsplit];
pipe_idx_unsplit 2772 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			dst->vupdate_width = context->bw_ctx.dml.vba.VUpdateWidthPix[pipe_idx_unsplit];
pipe_idx_unsplit 2773 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			dst->vready_offset = context->bw_ctx.dml.vba.VReadyOffsetPix[pipe_idx_unsplit];
pipe_idx_unsplit 2785 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 						dst_j->vstartup_start = context->bw_ctx.dml.vba.VStartup[pipe_idx_unsplit];
pipe_idx_unsplit 2786 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 						dst_j->vupdate_offset = context->bw_ctx.dml.vba.VUpdateOffsetPix[pipe_idx_unsplit];
pipe_idx_unsplit 2787 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 						dst_j->vupdate_width = context->bw_ctx.dml.vba.VUpdateWidthPix[pipe_idx_unsplit];
pipe_idx_unsplit 2788 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 						dst_j->vready_offset = context->bw_ctx.dml.vba.VReadyOffsetPix[pipe_idx_unsplit];
pipe_idx_unsplit 2793 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			pipe_idx_unsplit++;