pipe_idx 102 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c adev->pm.pm_display_cfg.displays[i].controller_id = dc_cfg->pipe_idx + 1; pipe_idx 515 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c int pipe_idx = secondary_pipe->pipe_idx; pipe_idx 522 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c secondary_pipe->pipe_idx = pipe_idx; pipe_idx 523 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx]; pipe_idx 524 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx]; pipe_idx 525 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c secondary_pipe->plane_res.ipp = pool->ipps[secondary_pipe->pipe_idx]; pipe_idx 526 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx]; pipe_idx 527 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx]; pipe_idx 528 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst; pipe_idx 148 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c cfg->pipe_idx = pipe_ctx->stream_res.tg->inst; pipe_idx 240 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c pp_display_cfg->disp_configs[0].pipe_idx; pipe_idx 1221 drivers/gpu/drm/amd/display/dc/core/dc.c context->res_ctx.pipe_ctx[i].pipe_idx = i; pipe_idx 1264 drivers/gpu/drm/amd/display/dc/core/dc.c cur_pipe->top_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx]; pipe_idx 1267 drivers/gpu/drm/amd/display/dc/core/dc.c cur_pipe->bottom_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx]; pipe_idx 1270 drivers/gpu/drm/amd/display/dc/core/dc.c cur_pipe->prev_odm_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->prev_odm_pipe->pipe_idx]; pipe_idx 1273 drivers/gpu/drm/amd/display/dc/core/dc.c cur_pipe->next_odm_pipe = &new_ctx->res_ctx.pipe_ctx[cur_pipe->next_odm_pipe->pipe_idx]; pipe_idx 325 drivers/gpu/drm/amd/display/dc/core/dc_debug.c if (pipe_ctx->stream == NULL || pipe_ctx->pipe_idx == underlay_idx) pipe_idx 335 drivers/gpu/drm/amd/display/dc/core/dc_debug.c if (pipe_ctx->stream == NULL || pipe_ctx->pipe_idx == underlay_idx) pipe_idx 2545 drivers/gpu/drm/amd/display/dc/core/dc_link.c pipe_ctx->pipe_idx); pipe_idx 2633 drivers/gpu/drm/amd/display/dc/core/dc_link.c pipe_ctx->pipe_idx); pipe_idx 1105 drivers/gpu/drm/amd/display/dc/core/dc_resource.c int preferred_pipe_idx = (pool->pipe_count - 1) - primary_pipe->pipe_idx; pipe_idx 1108 drivers/gpu/drm/amd/display/dc/core/dc_resource.c secondary_pipe->pipe_idx = preferred_pipe_idx; pipe_idx 1120 drivers/gpu/drm/amd/display/dc/core/dc_resource.c secondary_pipe->pipe_idx = i; pipe_idx 1220 drivers/gpu/drm/amd/display/dc/core/dc_resource.c split_pipe->pipe_idx = i; pipe_idx 1276 drivers/gpu/drm/amd/display/dc/core/dc_resource.c int pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream); pipe_idx 1277 drivers/gpu/drm/amd/display/dc/core/dc_resource.c if (pipe_idx >= 0) pipe_idx 1278 drivers/gpu/drm/amd/display/dc/core/dc_resource.c free_pipe = &context->res_ctx.pipe_ctx[pipe_idx]; pipe_idx 1625 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->pipe_idx = i; pipe_idx 1896 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx->pipe_idx = tg_inst; pipe_idx 1914 drivers/gpu/drm/amd/display/dc/core/dc_resource.c int pipe_idx = -1; pipe_idx 1938 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_idx = acquire_resource_from_hw_enabled_state( pipe_idx 1943 drivers/gpu/drm/amd/display/dc/core/dc_resource.c if (pipe_idx < 0) pipe_idx 1945 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_idx = acquire_first_free_pipe(&context->res_ctx, pool, stream); pipe_idx 1948 drivers/gpu/drm/amd/display/dc/core/dc_resource.c if (pipe_idx < 0) pipe_idx 1949 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream); pipe_idx 1952 drivers/gpu/drm/amd/display/dc/core/dc_resource.c if (pipe_idx < 0 || context->res_ctx.pipe_ctx[pipe_idx].stream_res.tg == NULL) pipe_idx 1955 drivers/gpu/drm/amd/display/dc/core/dc_resource.c pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx]; pipe_idx 2457 drivers/gpu/drm/amd/display/dc/core/dc_resource.c cur_pipe->top_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx]; pipe_idx 2460 drivers/gpu/drm/amd/display/dc/core/dc_resource.c cur_pipe->bottom_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx]; pipe_idx 2463 drivers/gpu/drm/amd/display/dc/core/dc_resource.c cur_pipe->next_odm_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->next_odm_pipe->pipe_idx]; pipe_idx 2466 drivers/gpu/drm/amd/display/dc/core/dc_resource.c cur_pipe->prev_odm_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->prev_odm_pipe->pipe_idx]; pipe_idx 520 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c cfg->pipe_idx = pipe_ctx->stream_res.tg->inst; pipe_idx 660 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c pp_display_cfg->disp_configs[0].pipe_idx; pipe_idx 1276 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx[pipe_ctx->pipe_idx]; pipe_idx 1514 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c dc->current_state->res_ctx.pipe_ctx[i].pipe_idx = i; pipe_idx 1792 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c uint32_t *pipe_idx) pipe_idx 1819 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (pipe_ctx->pipe_idx != underlay_idx) { pipe_idx 1820 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c *pipe_idx = i; pipe_idx 1858 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c uint32_t pipe_idx = 0; pipe_idx 1860 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (should_enable_fbc(dc, context, &pipe_idx)) { pipe_idx 1864 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx]; pipe_idx 2476 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c old_pipe = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx]; pipe_idx 2544 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->pipe_idx, pipe_idx 2565 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->pipe_idx, pipe_idx 2640 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->plane_res.mi->inst : pipe_ctx->pipe_idx; pipe_idx 858 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c if (pipe_ctx->pipe_idx != underlay_idx) pipe_idx 1066 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c pipe_ctx->pipe_idx = underlay_idx; pipe_idx 872 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst); pipe_idx 1073 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->pipe_idx); pipe_idx 1147 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->pipe_idx = i; pipe_idx 2621 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c old_pipe_ctx->pipe_idx); pipe_idx 1110 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx]; pipe_idx 1111 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx]; pipe_idx 1112 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]; pipe_idx 1113 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst; pipe_idx 520 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->pipe_idx); pipe_idx 1219 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c old_pipe_ctx->pipe_idx); pipe_idx 1690 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst); pipe_idx 2062 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->pipe_idx = i; pipe_idx 1534 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c int pipe_idx) pipe_idx 1542 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c *dsc = pool->dscs[pipe_idx]; pipe_idx 1543 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c res_ctx->is_dsc_acquired[pipe_idx] = true; pipe_idx 1728 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c int pipe_idx = next_odm_pipe->pipe_idx; pipe_idx 1732 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c next_odm_pipe->pipe_idx = pipe_idx; pipe_idx 1733 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c next_odm_pipe->plane_res.mi = pool->mis[next_odm_pipe->pipe_idx]; pipe_idx 1734 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c next_odm_pipe->plane_res.hubp = pool->hubps[next_odm_pipe->pipe_idx]; pipe_idx 1735 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c next_odm_pipe->plane_res.ipp = pool->ipps[next_odm_pipe->pipe_idx]; pipe_idx 1736 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c next_odm_pipe->plane_res.xfm = pool->transforms[next_odm_pipe->pipe_idx]; pipe_idx 1737 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c next_odm_pipe->plane_res.dpp = pool->dpps[next_odm_pipe->pipe_idx]; pipe_idx 1738 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c next_odm_pipe->plane_res.mpcc_inst = pool->dpps[next_odm_pipe->pipe_idx]->inst; pipe_idx 1787 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c next_odm_pipe->stream_res.opp = pool->opps[next_odm_pipe->pipe_idx]; pipe_idx 1790 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c acquire_dsc(res_ctx, pool, &next_odm_pipe->stream_res.dsc, next_odm_pipe->pipe_idx); pipe_idx 1806 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c int pipe_idx = secondary_pipe->pipe_idx; pipe_idx 1812 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c secondary_pipe->pipe_idx = pipe_idx; pipe_idx 1813 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx]; pipe_idx 1814 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx]; pipe_idx 1815 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c secondary_pipe->plane_res.ipp = pool->ipps[secondary_pipe->pipe_idx]; pipe_idx 1816 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx]; pipe_idx 1817 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx]; pipe_idx 1818 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst; pipe_idx 1947 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx; pipe_idx 1950 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].top_pipe->pipe_idx; pipe_idx 1956 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pipes[pipe_cnt].pipe.src.hsplit_grp = first_pipe->pipe_idx; pipe_idx 2306 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe) { pipe_idx 2307 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe->pipe_idx; pipe_idx 2310 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c secondary_pipe->pipe_idx = preferred_pipe_idx; pipe_idx 2312 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c } else if (dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe) { pipe_idx 2313 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe->pipe_idx; pipe_idx 2316 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c secondary_pipe->pipe_idx = preferred_pipe_idx; pipe_idx 2333 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c secondary_pipe->pipe_idx = preferred_pipe_idx; pipe_idx 2354 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c secondary_pipe->pipe_idx = preferred_pipe_idx; pipe_idx 2374 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c int pipe_cnt, i, pipe_idx, vlevel, vlevel_unsplit; pipe_idx 2517 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { pipe_idx 2521 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (context->bw_ctx.dml.vba.NoOfDPP[vlevel_unsplit][0][pipe_idx] == 1) pipe_idx 2523 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pipe_idx++; pipe_idx 2526 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) { pipe_idx 2535 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pipe_idx++; pipe_idx 2539 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx] = true; pipe_idx 2540 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_idx] = true; pipe_idx 2542 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (force_split && context->bw_ctx.dml.vba.NoOfDPP[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] == 1) pipe_idx 2543 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] /= 2; pipe_idx 2544 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { pipe_idx 2551 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx; pipe_idx 2575 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c need_split = context->bw_ctx.dml.vba.NoOfDPP[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] == 2; pipe_idx 2579 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) pipe_idx 2590 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { pipe_idx 2600 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx; pipe_idx 2635 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c int pipe_cnt, i, pipe_idx; pipe_idx 2637 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { pipe_idx 2646 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx]; pipe_idx 2647 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx) pipe_idx 2649 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_idx]; pipe_idx 2652 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pipe_idx++; pipe_idx 2675 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (pipe_cnt != pipe_idx) { pipe_idx 2740 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c int i, j, pipe_idx, pipe_idx_unsplit; pipe_idx 2762 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c for (i = 0, pipe_idx = 0, pipe_idx_unsplit = 0; i < dc->res_pool->pipe_count; i++) { pipe_idx 2766 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (!visited[pipe_idx]) { pipe_idx 2779 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c for (j = pipe_idx + 1; j < pipe_cnt; j++) { pipe_idx 2792 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c visited[pipe_idx] = true; pipe_idx 2795 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pipe_idx++; pipe_idx 2798 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { pipe_idx 2801 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) pipe_idx 2802 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000; pipe_idx 2804 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000; pipe_idx 2805 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c ASSERT(visited[pipe_idx]); pipe_idx 2806 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest; pipe_idx 2807 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pipe_idx++; pipe_idx 2815 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { pipe_idx 2826 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pipe_idx, pipe_idx 2833 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pipes[pipe_idx].pipe); pipe_idx 2834 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c pipe_idx++; pipe_idx 2953 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx]; pipe_idx 2954 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx]; pipe_idx 2955 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx]; pipe_idx 2956 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst; pipe_idx 986 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c int pipe_cnt, i, pipe_idx; pipe_idx 993 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { pipe_idx 1002 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx]; pipe_idx 1003 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx) pipe_idx 1005 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_idx]; pipe_idx 1008 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c pipe_idx++; pipe_idx 1021 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c if (pipe_cnt != pipe_idx) { pipe_idx 126 drivers/gpu/drm/amd/display/dc/dm_services_types.h uint8_t pipe_idx; pipe_idx 49 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c const unsigned int pipe_idx, pipe_idx 769 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c const unsigned int pipe_idx, pipe_idx 777 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src; pipe_idx 778 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest; pipe_idx 779 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout; pipe_idx 780 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; pipe_idx 781 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth; pipe_idx 782 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps; pipe_idx 927 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); pipe_idx 1016 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c double dsc_delay = get_dsc_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); pipe_idx 1062 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c dst_x_after_scaler = get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); pipe_idx 1063 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c dst_y_after_scaler = get_dst_y_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); pipe_idx 1086 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c dst_y_prefetch = get_dst_y_prefetch(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); pipe_idx 1092 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c pipe_idx); pipe_idx 1096 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c pipe_idx); pipe_idx 1097 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c dst_y_per_vm_flip = get_dst_y_per_vm_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); pipe_idx 1098 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c dst_y_per_row_flip = get_dst_y_per_row_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); pipe_idx 1121 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c vratio_pre_l = get_vratio_prefetch_l(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); pipe_idx 1122 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c vratio_pre_c = get_vratio_prefetch_c(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); pipe_idx 1349 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c xfc_transfer_delay = get_xfc_transfer_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); pipe_idx 1353 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c pipe_idx); pipe_idx 1357 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c pipe_idx); pipe_idx 1362 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c pipe_idx); pipe_idx 1568 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c const unsigned int pipe_idx, pipe_idx 1600 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c dml_print("DML_DLG: Calculation for pipe[%d] start\n\n", pipe_idx); pipe_idx 1601 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c dml20_rq_dlg_get_rq_params(mode_lib, &rq_param, e2e_pipe_param[pipe_idx].pipe.src); pipe_idx 1605 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c pipe_idx, pipe_idx 1612 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c dml_print("DML_DLG: Calculation for pipe[%d] end\n", pipe_idx); pipe_idx 67 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.h const unsigned int pipe_idx, pipe_idx 49 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c const unsigned int pipe_idx, pipe_idx 769 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c const unsigned int pipe_idx, pipe_idx 777 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src; pipe_idx 778 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest; pipe_idx 779 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout; pipe_idx 780 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; pipe_idx 781 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth; pipe_idx 782 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps; pipe_idx 927 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); pipe_idx 1016 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c double dsc_delay = get_dsc_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); pipe_idx 1062 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c dst_x_after_scaler = get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); pipe_idx 1063 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c dst_y_after_scaler = get_dst_y_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); pipe_idx 1086 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c dst_y_prefetch = get_dst_y_prefetch(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); pipe_idx 1092 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c pipe_idx); pipe_idx 1096 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c pipe_idx); pipe_idx 1097 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c dst_y_per_vm_flip = get_dst_y_per_vm_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); pipe_idx 1098 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c dst_y_per_row_flip = get_dst_y_per_row_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); pipe_idx 1121 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c vratio_pre_l = get_vratio_prefetch_l(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); pipe_idx 1122 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c vratio_pre_c = get_vratio_prefetch_c(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); pipe_idx 1349 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c xfc_transfer_delay = get_xfc_transfer_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); pipe_idx 1353 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c pipe_idx); pipe_idx 1357 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c pipe_idx); pipe_idx 1362 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c pipe_idx); pipe_idx 1568 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c const unsigned int pipe_idx, pipe_idx 1600 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c dml_print("DML_DLG: Calculation for pipe[%d] start\n\n", pipe_idx); pipe_idx 1601 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c dml20v2_rq_dlg_get_rq_params(mode_lib, &rq_param, e2e_pipe_param[pipe_idx].pipe.src); pipe_idx 1605 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c pipe_idx, pipe_idx 1612 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c dml_print("DML_DLG: Calculation for pipe[%d] end\n", pipe_idx); pipe_idx 67 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.h const unsigned int pipe_idx, pipe_idx 816 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c const unsigned int pipe_idx, pipe_idx 824 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src; pipe_idx 825 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest; pipe_idx 826 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout; pipe_idx 827 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; pipe_idx 828 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth; pipe_idx 829 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps; pipe_idx 974 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); pipe_idx 1056 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c double dsc_delay = get_dsc_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); pipe_idx 1105 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c dst_x_after_scaler = get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); pipe_idx 1106 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c dst_y_after_scaler = get_dst_y_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); pipe_idx 1134 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c dst_y_prefetch = get_dst_y_prefetch(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); pipe_idx 1141 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c pipe_idx); pipe_idx 1146 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c pipe_idx); pipe_idx 1147 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c dst_y_per_vm_flip = get_dst_y_per_vm_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); pipe_idx 1148 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c dst_y_per_row_flip = get_dst_y_per_row_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); pipe_idx 1173 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c vratio_pre_l = get_vratio_prefetch_l(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); pipe_idx 1174 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c vratio_pre_c = get_vratio_prefetch_c(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); pipe_idx 1417 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c xfc_transfer_delay = get_xfc_transfer_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); pipe_idx 1422 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c pipe_idx); pipe_idx 1427 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c pipe_idx); pipe_idx 1433 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c pipe_idx); pipe_idx 1524 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->refcyc_per_vm_group_vblank = get_refcyc_per_vm_group_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; pipe_idx 1525 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->refcyc_per_vm_group_flip = get_refcyc_per_vm_group_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; pipe_idx 1526 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->refcyc_per_vm_req_vblank = get_refcyc_per_vm_req_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz;; pipe_idx 1527 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->refcyc_per_vm_req_flip = get_refcyc_per_vm_req_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz;; pipe_idx 1669 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c const unsigned int pipe_idx, pipe_idx 1704 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c dml_print("DML_DLG: Calculation for pipe[%d] start\n\n", pipe_idx); pipe_idx 1705 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c dml_rq_dlg_get_rq_params(mode_lib, &rq_param, e2e_pipe_param[pipe_idx].pipe); pipe_idx 1710 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c pipe_idx, pipe_idx 1717 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c dml_print("DML_DLG: Calculation for pipe[%d] end\n", pipe_idx); pipe_idx 66 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.h const unsigned int pipe_idx, pipe_idx 55 drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h const unsigned int pipe_idx, pipe_idx 299 drivers/gpu/drm/amd/display/dc/inc/core_types.h uint8_t pipe_idx;