pipe_dlg_param 434 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c input->dest.vstartup_start = pipe->pipe_dlg_param.vstartup_start; pipe_dlg_param 435 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset; pipe_dlg_param 436 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset; pipe_dlg_param 437 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c input->dest.vupdate_width = pipe->pipe_dlg_param.vupdate_width; pipe_dlg_param 1181 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c pipe->pipe_dlg_param.vupdate_width = v->v_update_width_pix[input_idx]; pipe_dlg_param 1182 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c pipe->pipe_dlg_param.vupdate_offset = v->v_update_offset_pix[input_idx]; pipe_dlg_param 1183 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c pipe->pipe_dlg_param.vready_offset = v->v_ready_offset_pix[input_idx]; pipe_dlg_param 1184 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c pipe->pipe_dlg_param.vstartup_start = v->v_startup[input_idx]; pipe_dlg_param 1186 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c pipe->pipe_dlg_param.htotal = pipe->stream->timing.h_total; pipe_dlg_param 1187 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c pipe->pipe_dlg_param.vtotal = pipe->stream->timing.v_total; pipe_dlg_param 1203 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c pipe->pipe_dlg_param.vblank_start = asic_blank_start; pipe_dlg_param 1204 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c pipe->pipe_dlg_param.vblank_end = asic_blank_end; pipe_dlg_param 1222 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c hsplit_pipe->pipe_dlg_param.vupdate_width = v->v_update_width_pix[input_idx]; pipe_dlg_param 1223 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c hsplit_pipe->pipe_dlg_param.vupdate_offset = v->v_update_offset_pix[input_idx]; pipe_dlg_param 1224 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c hsplit_pipe->pipe_dlg_param.vready_offset = v->v_ready_offset_pix[input_idx]; pipe_dlg_param 1225 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c hsplit_pipe->pipe_dlg_param.vstartup_start = v->v_startup[input_idx]; pipe_dlg_param 1227 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c hsplit_pipe->pipe_dlg_param.htotal = pipe->stream->timing.h_total; pipe_dlg_param 1228 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c hsplit_pipe->pipe_dlg_param.vtotal = pipe->stream->timing.v_total; pipe_dlg_param 1229 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c hsplit_pipe->pipe_dlg_param.vblank_start = pipe->pipe_dlg_param.vblank_start; pipe_dlg_param 1230 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c hsplit_pipe->pipe_dlg_param.vblank_end = pipe->pipe_dlg_param.vblank_end; pipe_dlg_param 765 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->pipe_dlg_param.vready_offset, pipe_dlg_param 766 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->pipe_dlg_param.vstartup_start, pipe_dlg_param 767 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->pipe_dlg_param.vupdate_offset, pipe_dlg_param 768 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->pipe_dlg_param.vupdate_width, pipe_dlg_param 2327 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c &pipe_ctx->pipe_dlg_param); pipe_dlg_param 2507 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->pipe_dlg_param.vready_offset, pipe_dlg_param 2508 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->pipe_dlg_param.vstartup_start, pipe_dlg_param 2509 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->pipe_dlg_param.vupdate_offset, pipe_dlg_param 2510 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->pipe_dlg_param.vupdate_width); pipe_dlg_param 3099 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c pipe_ctx->pipe_dlg_param.vstartup_start + 1; pipe_dlg_param 571 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->pipe_dlg_param.vready_offset, pipe_dlg_param 572 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->pipe_dlg_param.vstartup_start, pipe_dlg_param 573 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->pipe_dlg_param.vupdate_offset, pipe_dlg_param 574 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->pipe_dlg_param.vupdate_width, pipe_dlg_param 1041 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->pipe_dlg_param.vready_offset, pipe_dlg_param 1042 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->pipe_dlg_param.vstartup_start, pipe_dlg_param 1043 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->pipe_dlg_param.vupdate_offset, pipe_dlg_param 1044 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->pipe_dlg_param.vupdate_width); pipe_dlg_param 1333 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->pipe_dlg_param.vready_offset, pipe_dlg_param 1334 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->pipe_dlg_param.vstartup_start, pipe_dlg_param 1335 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->pipe_dlg_param.vupdate_offset, pipe_dlg_param 1336 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->pipe_dlg_param.vupdate_width); pipe_dlg_param 1349 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c &pipe_ctx->pipe_dlg_param); pipe_dlg_param 2806 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest; pipe_dlg_param 310 drivers/gpu/drm/amd/display/dc/inc/core_types.h struct _vcs_dpi_display_pipe_dest_params_st pipe_dlg_param;