pipe_dest 119 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest) pipe_dest 131 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c if ((pipe_dest->vstartup_start - 2*(pipe_dest->vready_offset+pipe_dest->vupdate_width pipe_dest 132 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c + pipe_dest->vupdate_offset) / pipe_dest->htotal) <= pipe_dest->vblank_end) { pipe_dest 669 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest) pipe_dest 676 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c hubp1_vready_workaround(hubp, pipe_dest); pipe_dest 744 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest); pipe_dest 169 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest) pipe_dest 182 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c if ((pipe_dest->vstartup_start - (pipe_dest->vready_offset+pipe_dest->vupdate_width pipe_dest 183 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c + pipe_dest->vupdate_offset) / pipe_dest->htotal) <= pipe_dest->vblank_end) { pipe_dest 228 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest) pipe_dest 234 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c hubp2_vready_at_or_After_vsync(hubp, pipe_dest); pipe_dest 246 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest); pipe_dest 153 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest) pipe_dest 159 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c hubp2_vready_at_or_After_vsync(hubp, pipe_dest); pipe_dest 74 drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest); pipe_dest 98 drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest);