pipe_count       2760 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 	const struct pipe_ctx pipe[], int pipe_count, struct bw_calcs_data *data)
pipe_count       2776 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 	for (i = 0; i < pipe_count; i++) {
pipe_count       2886 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 	for (i = 0; i < pipe_count; i++) {
pipe_count       2982 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 				 int pipe_count)
pipe_count       2987 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 	for (i = 0; i < pipe_count; i++) {
pipe_count       3018 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 	int pipe_count,
pipe_count       3026 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 	populate_initial_data(pipe, pipe_count, data);
pipe_count       3029 drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c 		calcs_output->all_displays_in_sync = all_displays_in_sync(pipe, pipe_count);
pipe_count        865 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	for (i = 0, input_idx = 0; i < pool->pipe_count; i++) {
pipe_count       1171 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 		for (i = 0, input_idx = 0; i < pool->pipe_count; i++) {
pipe_count        101 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
pipe_count        107 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 	for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
pipe_count        281 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 			for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
pipe_count        298 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 			for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
pipe_count        754 drivers/gpu/drm/amd/display/dc/core/dc.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
pipe_count        797 drivers/gpu/drm/amd/display/dc/core/dc.c 	full_pipe_count = dc->res_pool->pipe_count;
pipe_count        846 drivers/gpu/drm/amd/display/dc/core/dc.c 	int pipe_count = dc->res_pool->pipe_count;
pipe_count        849 drivers/gpu/drm/amd/display/dc/core/dc.c 	for (i = 0; i < pipe_count; i++) {
pipe_count        872 drivers/gpu/drm/amd/display/dc/core/dc.c 	int pipe_count = dc->res_pool->pipe_count;
pipe_count        875 drivers/gpu/drm/amd/display/dc/core/dc.c 	for (i = 0; i < pipe_count; i++) {
pipe_count        882 drivers/gpu/drm/amd/display/dc/core/dc.c 	for (i = 0; i < pipe_count; i++) {
pipe_count        895 drivers/gpu/drm/amd/display/dc/core/dc.c 		for (j = i + 1; j < pipe_count; j++) {
pipe_count        991 drivers/gpu/drm/amd/display/dc/core/dc.c 	if (enc_inst >= dc->res_pool->pipe_count)
pipe_count       1093 drivers/gpu/drm/amd/display/dc/core/dc.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
pipe_count       1218 drivers/gpu/drm/amd/display/dc/core/dc.c 	for (i = 0; i < dc->res_pool->pipe_count; i++)
pipe_count       1902 drivers/gpu/drm/amd/display/dc/core/dc.c 	for (j = 0; j < dc->res_pool->pipe_count; j++) {
pipe_count       2041 drivers/gpu/drm/amd/display/dc/core/dc.c 			for (j = 0; j < dc->res_pool->pipe_count; j++) {
pipe_count       2061 drivers/gpu/drm/amd/display/dc/core/dc.c 	for (j = 0; j < dc->res_pool->pipe_count; j++) {
pipe_count       2110 drivers/gpu/drm/amd/display/dc/core/dc.c 				for (j = 0; j < dc->res_pool->pipe_count; j++) {
pipe_count       2129 drivers/gpu/drm/amd/display/dc/core/dc.c 			for (j = 0; j < dc->res_pool->pipe_count; j++) {
pipe_count       2155 drivers/gpu/drm/amd/display/dc/core/dc.c 	for (j = 0; j < dc->res_pool->pipe_count; j++) {
pipe_count       2203 drivers/gpu/drm/amd/display/dc/core/dc.c 		for (i = 0; i < dc->res_pool->pipe_count; i++) {
pipe_count       2219 drivers/gpu/drm/amd/display/dc/core/dc.c 			for (j = 0; j < dc->res_pool->pipe_count; j++) {
pipe_count       2249 drivers/gpu/drm/amd/display/dc/core/dc.c 		for (i = 0; i < dc->res_pool->pipe_count; i++) {
pipe_count        320 drivers/gpu/drm/amd/display/dc/core/dc_debug.c 	for (i = 0; i < core_dc->res_pool->pipe_count; i++) {
pipe_count        332 drivers/gpu/drm/amd/display/dc/core/dc_debug.c 	for (i = 0; i < core_dc->res_pool->pipe_count; i++) {
pipe_count       1105 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		int preferred_pipe_idx = (pool->pipe_count - 1) - primary_pipe->pipe_idx;
pipe_count       1117 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		for (i = pool->pipe_count - 1; i >= 0; i--) {
pipe_count       1175 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	for (i = pool->pipe_count - 1; i >= 0; i--) {
pipe_count       1201 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	for (i = 0; i < pool->pipe_count; i++) {
pipe_count       1330 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	for (i = pool->pipe_count - 1; i >= 0; i--) {
pipe_count       1612 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	for (i = 0; i < pool->pipe_count; i++) {
pipe_count       1872 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 	if (inst >= pool->pipe_count)
pipe_count       2054 drivers/gpu/drm/amd/display/dc/core/dc_resource.c 		for (j = 0; j < dc->res_pool->pipe_count; j++) {
pipe_count        161 drivers/gpu/drm/amd/display/dc/core/dc_surface.c 	for (i = 0; i < core_dc->res_pool->pipe_count; i++) {
pipe_count        173 drivers/gpu/drm/amd/display/dc/core/dc_surface.c 	for (i = 0; i < core_dc->res_pool->pipe_count; i++) {
pipe_count        686 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 	for (i = 0; i < pool->base.pipe_count; i++) {
pipe_count        773 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
pipe_count        993 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 	pool->base.pipe_count = res_cap.num_timing_generator;
pipe_count       1000 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 	for (i = 0; i < pool->base.pipe_count; i++) {
pipe_count       1063 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c 	dc->caps.max_planes =  pool->base.pipe_count;
pipe_count       1508 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
pipe_count       1810 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
pipe_count       1826 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	if (i == dc->res_pool->pipe_count)
pipe_count       1973 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
pipe_count       2000 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	if (i == dc->res_pool->pipe_count) {
pipe_count       2001 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 		for (i = 0; i < dc->res_pool->pipe_count; i++) {
pipe_count       2049 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
pipe_count       2074 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
pipe_count       2375 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
pipe_count       2403 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
pipe_count       2590 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
pipe_count       2601 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
pipe_count       2623 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
pipe_count        743 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 	for (i = 0; i < pool->base.pipe_count; i++) {
pipe_count        906 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 			dc->res_pool->pipe_count,
pipe_count       1192 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 	pool->opps[pool->pipe_count] = &dce110_oppv->base;
pipe_count       1193 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 	pool->timing_generators[pool->pipe_count] = &dce110_tgv->base;
pipe_count       1194 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 	pool->mis[pool->pipe_count] = &dce110_miv->base;
pipe_count       1195 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 	pool->transforms[pool->pipe_count] = &dce110_xfmv->base;
pipe_count       1196 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 	pool->pipe_count++;
pipe_count       1289 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 	pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
pipe_count       1290 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 	pool->base.underlay_pipe_index = pool->base.pipe_count;
pipe_count       1361 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 	for (i = 0; i < pool->base.pipe_count; i++) {
pipe_count       1434 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c 	dc->caps.max_planes =  pool->base.pipe_count;
pipe_count        705 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 	for (i = 0; i < pool->base.pipe_count; i++) {
pipe_count        828 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 			dc->res_pool->pipe_count,
pipe_count       1160 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 	pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
pipe_count       1245 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 	for (i = 0; i < pool->base.pipe_count; i++) {
pipe_count       1314 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c 	dc->caps.max_planes =  pool->base.pipe_count;
pipe_count        552 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 	for (i = 0; i < pool->base.pipe_count; i++) {
pipe_count       1000 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 	pool->base.pipe_count = res_cap.num_timing_generator;
pipe_count       1087 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 	for (i = 0; i < pool->base.pipe_count; i++) {
pipe_count       1163 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 	pool->base.pipe_count = j;
pipe_count       1178 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 	dc->caps.max_planes =  pool->base.pipe_count;
pipe_count        734 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	for (i = 0; i < pool->base.pipe_count; i++) {
pipe_count        807 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
pipe_count        892 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	pool->base.pipe_count = res_cap.num_timing_generator;
pipe_count        970 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	for (i = 0; i < pool->base.pipe_count; i++) {
pipe_count       1032 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	dc->caps.max_planes =  pool->base.pipe_count;
pipe_count       1089 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	pool->base.pipe_count = res_cap_81.num_timing_generator;
pipe_count       1167 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	for (i = 0; i < pool->base.pipe_count; i++) {
pipe_count       1229 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	dc->caps.max_planes =  pool->base.pipe_count;
pipe_count       1286 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	pool->base.pipe_count = res_cap_83.num_timing_generator;
pipe_count       1360 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	for (i = 0; i < pool->base.pipe_count; i++) {
pipe_count       1422 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c 	dc->caps.max_planes =  pool->base.pipe_count;
pipe_count        135 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	for (i = 0; i < pool->pipe_count; i++) {
pipe_count        167 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	for (i = 0; i < pool->pipe_count; i++) {
pipe_count        192 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	for (i = 0; i < pool->pipe_count; i++) {
pipe_count        224 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	for (i = 0; i < pool->pipe_count; i++) {
pipe_count        257 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	for (i = 0; i < pool->pipe_count; i++) {
pipe_count        299 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	for (i = 0; i < pool->pipe_count; i++) {
pipe_count        649 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
pipe_count        689 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
pipe_count        715 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
pipe_count        863 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++)
pipe_count        867 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	if (i == dc->res_pool->pipe_count)
pipe_count        884 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
pipe_count        909 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
pipe_count        922 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
pipe_count        932 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
pipe_count        944 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
pipe_count       1088 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
pipe_count       1114 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
pipe_count       1125 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
pipe_count       1312 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
pipe_count       2533 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
pipe_count       2595 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
pipe_count       2634 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 		for (i = 0; i < dc->res_pool->pipe_count; i++) {
pipe_count       2655 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++)
pipe_count       2659 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++)
pipe_count       2875 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	for (i = 0; i < res_pool->pipe_count; i++) {
pipe_count       3112 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
pipe_count        133 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 	for (i = 0; i < pool->pipe_count; i++) {
pipe_count        203 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 	for (i = 0; i < pool->pipe_count; i++) {
pipe_count        248 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 	for (i = 0; i < pool->pipe_count; i++) {
pipe_count        302 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 	for (i = 0; i < pool->pipe_count; i++) {
pipe_count        341 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 	for (i = 0; i < pool->pipe_count; i++) {
pipe_count        394 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 	for (i = 0; i < pool->pipe_count; i++) {
pipe_count        509 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 	for (i = 0; i < pool->pipe_count; i++) {
pipe_count        906 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	for (i = 0; i < pool->base.pipe_count; i++) {
pipe_count       1300 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
pipe_count       1303 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 		pool->base.pipe_count = 3;
pipe_count       1447 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	for (i = 0; i < pool->base.pipe_count; i++) {
pipe_count       1516 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	pool->base.pipe_count = j;
pipe_count       1522 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	dc->dml.ip.max_num_dpp = pool->base.pipe_count;
pipe_count       1523 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	dc->dcn_ip->max_num_dpp = pool->base.pipe_count;
pipe_count       1545 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 	dc->caps.max_planes =  pool->base.pipe_count;
pipe_count        125 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c 	switch (dccg_dcn->base.ctx->dc->res_pool->pipe_count) {
pipe_count       1166 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
pipe_count       1193 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
pipe_count       1231 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 		for (i = 0; i < dc->res_pool->pipe_count; i++) {
pipe_count       1250 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	for (i = 0; i < dc->res_pool->pipe_count; i++)
pipe_count       1322 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
pipe_count       1681 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	for (i = 0; i < dc->res_pool->pipe_count; i++)
pipe_count       1685 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	if (i == dc->res_pool->pipe_count)
pipe_count       1700 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
pipe_count       2038 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
pipe_count       2055 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
pipe_count       2093 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
pipe_count       1330 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	for (i = 0; i < pool->base.pipe_count; i++) {
pipe_count       1583 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
pipe_count       1840 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
pipe_count       1878 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	for (i = 0, pipe_cnt = -1; i < dc->res_pool->pipe_count; i++) {
pipe_count       1894 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
pipe_count       2211 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
pipe_count       2258 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
pipe_count       2327 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) {
pipe_count       2349 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) {
pipe_count       2380 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	int split_threshold = dc->res_pool->pipe_count / 2;
pipe_count       2389 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
pipe_count       2420 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
pipe_count       2486 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
pipe_count       2517 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
pipe_count       2526 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {
pipe_count       2637 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
pipe_count       2762 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	for (i = 0, pipe_idx = 0, pipe_idx_unsplit = 0; i < dc->res_pool->pipe_count; i++) {
pipe_count       2798 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
pipe_count       2815 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
pipe_count       2848 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
pipe_count       3020 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	uint32_t pipe_count = pool->res_cap->num_dwb;
pipe_count       3022 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	ASSERT(pipe_count > 0);
pipe_count       3024 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	for (i = 0; i < pipe_count; i++) {
pipe_count       3045 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	uint32_t pipe_count = pool->res_cap->num_dwb;
pipe_count       3047 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	ASSERT(pipe_count > 0);
pipe_count       3049 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	for (i = 0; i < pipe_count; i++) {
pipe_count       3425 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	loaded_ip->max_num_dpp = pool->base.pipe_count;
pipe_count       3451 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		pool->base.pipe_count = 5;
pipe_count       3455 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		pool->base.pipe_count = 6;
pipe_count       3476 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		pool->base.pipe_count = 4;
pipe_count       3477 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		pool->base.mpcc_count = pool->base.pipe_count;
pipe_count       3618 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	for (i = 0; i < pool->base.pipe_count; i++) {
pipe_count       3726 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 	dc->caps.max_planes =  pool->base.pipe_count;
pipe_count        858 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 	for (i = 0; i < pool->base.pipe_count; i++) {
pipe_count        993 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 	for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
pipe_count       1072 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 	display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
pipe_count       1281 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 	dcn2_1_ip.max_num_dpp = pool->base.pipe_count;
pipe_count       1462 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 	pool->base.pipe_count = 4;
pipe_count       1476 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 		pool->base.pipe_count = 4;
pipe_count       1547 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 	for (i = 0; i < pool->base.pipe_count; i++) {
pipe_count       1656 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 	dc->caps.max_planes =  pool->base.pipe_count;
pipe_count        195 drivers/gpu/drm/amd/display/dc/inc/core_types.h 	unsigned int pipe_count;
pipe_count        485 drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h 	int pipe_count,
pipe_count       1267 kernel/rcu/rcutorture.c 	int pipe_count;
pipe_count       1292 kernel/rcu/rcutorture.c 	pipe_count = p->rtort_pipe_count;
pipe_count       1293 kernel/rcu/rcutorture.c 	if (pipe_count > RCU_TORTURE_PIPE_LEN) {
pipe_count       1295 kernel/rcu/rcutorture.c 		pipe_count = RCU_TORTURE_PIPE_LEN;
pipe_count       1298 kernel/rcu/rcutorture.c 	if (pipe_count > 1) {
pipe_count       1303 kernel/rcu/rcutorture.c 	__this_cpu_inc(rcu_torture_count[pipe_count]);
pipe_count       1315 kernel/rcu/rcutorture.c 	if ((pipe_count > 1 || completed > 1) && !xchg(&err_segs_recorded, 1)) {
pipe_count        101 sound/pci/mixart/mixart.c 	group_state.pipe_count = 1;
pipe_count        124 sound/pci/mixart/mixart.c 		group_state.pipe_count = 0; /* in case of start same command once again with pipe_count=0 */
pipe_count        567 sound/pci/mixart/mixart.c 	stream_param.pipe_count = 1;      /* set to 1 */
pipe_count        232 sound/pci/mixart/mixart_core.h 	u32           pipe_count;    /* set to 1 for instance */
pipe_count        394 sound/pci/mixart/mixart_core.h 	u32 pipe_count;                           /* set to 1 (array size !) */