pipe_config 1842 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c u32 pipe_config; pipe_config 1880 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); pipe_config 1996 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c pipe_config); pipe_config 1884 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c u32 pipe_config; pipe_config 1922 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); pipe_config 2038 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c pipe_config); pipe_config 1798 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c uint32_t fb_format, fb_pitch_pixels, pipe_config; pipe_config 1936 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); pipe_config 1937 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c fb_format |= GRPH_PIPE_CONFIG(pipe_config); pipe_config 1771 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c u32 pipe_config; pipe_config 1809 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); pipe_config 1911 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c fb_format |= (pipe_config << GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT); pipe_config 2848 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c tiling_info->gfx8.pipe_config = pipe_config 162 drivers/gpu/drm/amd/display/dc/core/dc_debug.c plane_state->tiling_info.gfx8.pipe_config, pipe_config 251 drivers/gpu/drm/amd/display/dc/core/dc_debug.c update->plane_info->tiling_info.gfx8.pipe_config, pipe_config 367 drivers/gpu/drm/amd/display/dc/dc_hw_types.h unsigned int pipe_config; pipe_config 380 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c GRPH_PIPE_CONFIG, info->gfx8.pipe_config, pipe_config 189 drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c set_reg_field_value(value, info->gfx8.pipe_config, pipe_config 266 drivers/gpu/drm/i915/display/icl_dsi.c const struct intel_crtc_state *pipe_config) pipe_config 279 drivers/gpu/drm/i915/display/icl_dsi.c &pipe_config->base.adjusted_mode; pipe_config 624 drivers/gpu/drm/i915/display/icl_dsi.c const struct intel_crtc_state *pipe_config) pipe_config 628 drivers/gpu/drm/i915/display/icl_dsi.c struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); pipe_config 722 drivers/gpu/drm/i915/display/icl_dsi.c configure_dual_link_mode(encoder, pipe_config); pipe_config 766 drivers/gpu/drm/i915/display/icl_dsi.c const struct intel_crtc_state *pipe_config) pipe_config 771 drivers/gpu/drm/i915/display/icl_dsi.c &pipe_config->base.adjusted_mode; pipe_config 958 drivers/gpu/drm/i915/display/icl_dsi.c const struct intel_crtc_state *pipe_config) pipe_config 981 drivers/gpu/drm/i915/display/icl_dsi.c gen11_dsi_configure_transcoder(encoder, pipe_config); pipe_config 1028 drivers/gpu/drm/i915/display/icl_dsi.c const struct intel_crtc_state *pipe_config, pipe_config 1039 drivers/gpu/drm/i915/display/icl_dsi.c const struct intel_crtc_state *pipe_config, pipe_config 1045 drivers/gpu/drm/i915/display/icl_dsi.c gen11_dsi_map_pll(encoder, pipe_config); pipe_config 1048 drivers/gpu/drm/i915/display/icl_dsi.c gen11_dsi_enable_port_and_phy(encoder, pipe_config); pipe_config 1054 drivers/gpu/drm/i915/display/icl_dsi.c gen11_dsi_set_transcoder_timings(encoder, pipe_config); pipe_config 1060 drivers/gpu/drm/i915/display/icl_dsi.c intel_panel_enable_backlight(pipe_config, conn_state); pipe_config 1215 drivers/gpu/drm/i915/display/icl_dsi.c struct intel_crtc_state *pipe_config) pipe_config 1219 drivers/gpu/drm/i915/display/icl_dsi.c &pipe_config->base.adjusted_mode; pipe_config 1242 drivers/gpu/drm/i915/display/icl_dsi.c struct intel_crtc_state *pipe_config) pipe_config 1245 drivers/gpu/drm/i915/display/icl_dsi.c struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); pipe_config 1249 drivers/gpu/drm/i915/display/icl_dsi.c pipe_config->port_clock = pipe_config 1250 drivers/gpu/drm/i915/display/icl_dsi.c cnl_calc_wrpll_link(dev_priv, &pipe_config->dpll_hw_state); pipe_config 1252 drivers/gpu/drm/i915/display/icl_dsi.c pipe_config->base.adjusted_mode.crtc_clock = intel_dsi->pclk; pipe_config 1254 drivers/gpu/drm/i915/display/icl_dsi.c pipe_config->base.adjusted_mode.crtc_clock *= 2; pipe_config 1256 drivers/gpu/drm/i915/display/icl_dsi.c gen11_dsi_get_timings(encoder, pipe_config); pipe_config 1257 drivers/gpu/drm/i915/display/icl_dsi.c pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI); pipe_config 1258 drivers/gpu/drm/i915/display/icl_dsi.c pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc); pipe_config 1262 drivers/gpu/drm/i915/display/icl_dsi.c struct intel_crtc_state *pipe_config, pipe_config 1268 drivers/gpu/drm/i915/display/icl_dsi.c struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); pipe_config 1272 drivers/gpu/drm/i915/display/icl_dsi.c &pipe_config->base.adjusted_mode; pipe_config 1274 drivers/gpu/drm/i915/display/icl_dsi.c pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; pipe_config 1276 drivers/gpu/drm/i915/display/icl_dsi.c intel_pch_panel_fitting(crtc, pipe_config, conn_state->scaling_mode); pipe_config 1282 drivers/gpu/drm/i915/display/icl_dsi.c pipe_config->cpu_transcoder = TRANSCODER_DSI_1; pipe_config 1284 drivers/gpu/drm/i915/display/icl_dsi.c pipe_config->cpu_transcoder = TRANSCODER_DSI_0; pipe_config 1286 drivers/gpu/drm/i915/display/icl_dsi.c pipe_config->clock_set = true; pipe_config 1287 drivers/gpu/drm/i915/display/icl_dsi.c pipe_config->port_clock = intel_dsi_bitrate(intel_dsi) / 5; pipe_config 131 drivers/gpu/drm/i915/display/intel_crt.c struct intel_crtc_state *pipe_config) pipe_config 133 drivers/gpu/drm/i915/display/intel_crt.c pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); pipe_config 135 drivers/gpu/drm/i915/display/intel_crt.c pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder); pipe_config 137 drivers/gpu/drm/i915/display/intel_crt.c pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock; pipe_config 141 drivers/gpu/drm/i915/display/intel_crt.c struct intel_crtc_state *pipe_config) pipe_config 145 drivers/gpu/drm/i915/display/intel_crt.c intel_ddi_get_config(encoder, pipe_config); pipe_config 147 drivers/gpu/drm/i915/display/intel_crt.c pipe_config->base.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC | pipe_config 151 drivers/gpu/drm/i915/display/intel_crt.c pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder); pipe_config 153 drivers/gpu/drm/i915/display/intel_crt.c pipe_config->base.adjusted_mode.crtc_clock = lpt_get_iclkip(dev_priv); pipe_config 357 drivers/gpu/drm/i915/display/intel_crt.c struct intel_crtc_state *pipe_config, pipe_config 361 drivers/gpu/drm/i915/display/intel_crt.c &pipe_config->base.adjusted_mode; pipe_config 366 drivers/gpu/drm/i915/display/intel_crt.c pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; pipe_config 372 drivers/gpu/drm/i915/display/intel_crt.c struct intel_crtc_state *pipe_config, pipe_config 376 drivers/gpu/drm/i915/display/intel_crt.c &pipe_config->base.adjusted_mode; pipe_config 381 drivers/gpu/drm/i915/display/intel_crt.c pipe_config->has_pch_encoder = true; pipe_config 382 drivers/gpu/drm/i915/display/intel_crt.c pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; pipe_config 388 drivers/gpu/drm/i915/display/intel_crt.c struct intel_crtc_state *pipe_config, pipe_config 393 drivers/gpu/drm/i915/display/intel_crt.c &pipe_config->base.adjusted_mode; pipe_config 403 drivers/gpu/drm/i915/display/intel_crt.c pipe_config->has_pch_encoder = true; pipe_config 404 drivers/gpu/drm/i915/display/intel_crt.c pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; pipe_config 408 drivers/gpu/drm/i915/display/intel_crt.c if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) { pipe_config 413 drivers/gpu/drm/i915/display/intel_crt.c pipe_config->pipe_bpp = 24; pipe_config 417 drivers/gpu/drm/i915/display/intel_crt.c pipe_config->port_clock = 135000 * 2; pipe_config 1460 drivers/gpu/drm/i915/display/intel_ddi.c static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) pipe_config 1464 drivers/gpu/drm/i915/display/intel_ddi.c if (pipe_config->has_pch_encoder) pipe_config 1465 drivers/gpu/drm/i915/display/intel_ddi.c dotclock = intel_dotclock_calculate(pipe_config->port_clock, pipe_config 1466 drivers/gpu/drm/i915/display/intel_ddi.c &pipe_config->fdi_m_n); pipe_config 1467 drivers/gpu/drm/i915/display/intel_ddi.c else if (intel_crtc_has_dp_encoder(pipe_config)) pipe_config 1468 drivers/gpu/drm/i915/display/intel_ddi.c dotclock = intel_dotclock_calculate(pipe_config->port_clock, pipe_config 1469 drivers/gpu/drm/i915/display/intel_ddi.c &pipe_config->dp_m_n); pipe_config 1470 drivers/gpu/drm/i915/display/intel_ddi.c else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24) pipe_config 1471 drivers/gpu/drm/i915/display/intel_ddi.c dotclock = pipe_config->port_clock * 24 / pipe_config->pipe_bpp; pipe_config 1473 drivers/gpu/drm/i915/display/intel_ddi.c dotclock = pipe_config->port_clock; pipe_config 1475 drivers/gpu/drm/i915/display/intel_ddi.c if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 && pipe_config 1476 drivers/gpu/drm/i915/display/intel_ddi.c !intel_crtc_has_dp_encoder(pipe_config)) pipe_config 1479 drivers/gpu/drm/i915/display/intel_ddi.c if (pipe_config->pixel_multiplier) pipe_config 1480 drivers/gpu/drm/i915/display/intel_ddi.c dotclock /= pipe_config->pixel_multiplier; pipe_config 1482 drivers/gpu/drm/i915/display/intel_ddi.c pipe_config->base.adjusted_mode.crtc_clock = dotclock; pipe_config 1486 drivers/gpu/drm/i915/display/intel_ddi.c struct intel_crtc_state *pipe_config) pipe_config 1489 drivers/gpu/drm/i915/display/intel_ddi.c struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state; pipe_config 1498 drivers/gpu/drm/i915/display/intel_ddi.c pipe_config->shared_dpll); pipe_config 1506 drivers/gpu/drm/i915/display/intel_ddi.c pipe_config->port_clock = link_clock; pipe_config 1508 drivers/gpu/drm/i915/display/intel_ddi.c ddi_dotclock_get(pipe_config); pipe_config 1512 drivers/gpu/drm/i915/display/intel_ddi.c struct intel_crtc_state *pipe_config) pipe_config 1515 drivers/gpu/drm/i915/display/intel_ddi.c struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state; pipe_config 1555 drivers/gpu/drm/i915/display/intel_ddi.c pipe_config->port_clock = link_clock; pipe_config 1557 drivers/gpu/drm/i915/display/intel_ddi.c ddi_dotclock_get(pipe_config); pipe_config 1561 drivers/gpu/drm/i915/display/intel_ddi.c struct intel_crtc_state *pipe_config) pipe_config 1563 drivers/gpu/drm/i915/display/intel_ddi.c struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state; pipe_config 1602 drivers/gpu/drm/i915/display/intel_ddi.c pipe_config->port_clock = link_clock; pipe_config 1604 drivers/gpu/drm/i915/display/intel_ddi.c ddi_dotclock_get(pipe_config); pipe_config 1608 drivers/gpu/drm/i915/display/intel_ddi.c struct intel_crtc_state *pipe_config) pipe_config 1614 drivers/gpu/drm/i915/display/intel_ddi.c val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll); pipe_config 1649 drivers/gpu/drm/i915/display/intel_ddi.c pipe_config->port_clock = link_clock * 2; pipe_config 1651 drivers/gpu/drm/i915/display/intel_ddi.c ddi_dotclock_get(pipe_config); pipe_config 1670 drivers/gpu/drm/i915/display/intel_ddi.c struct intel_crtc_state *pipe_config) pipe_config 1672 drivers/gpu/drm/i915/display/intel_ddi.c pipe_config->port_clock = pipe_config 1673 drivers/gpu/drm/i915/display/intel_ddi.c bxt_calc_pll_link(&pipe_config->dpll_hw_state); pipe_config 1675 drivers/gpu/drm/i915/display/intel_ddi.c ddi_dotclock_get(pipe_config); pipe_config 1679 drivers/gpu/drm/i915/display/intel_ddi.c struct intel_crtc_state *pipe_config) pipe_config 1684 drivers/gpu/drm/i915/display/intel_ddi.c icl_ddi_clock_get(encoder, pipe_config); pipe_config 1686 drivers/gpu/drm/i915/display/intel_ddi.c cnl_ddi_clock_get(encoder, pipe_config); pipe_config 1688 drivers/gpu/drm/i915/display/intel_ddi.c bxt_ddi_clock_get(encoder, pipe_config); pipe_config 1690 drivers/gpu/drm/i915/display/intel_ddi.c skl_ddi_clock_get(encoder, pipe_config); pipe_config 1692 drivers/gpu/drm/i915/display/intel_ddi.c hsw_ddi_clock_get(encoder, pipe_config); pipe_config 3828 drivers/gpu/drm/i915/display/intel_ddi.c struct intel_crtc_state *pipe_config) pipe_config 3831 drivers/gpu/drm/i915/display/intel_ddi.c struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); pipe_config 3832 drivers/gpu/drm/i915/display/intel_ddi.c enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; pipe_config 3849 drivers/gpu/drm/i915/display/intel_ddi.c pipe_config->base.adjusted_mode.flags |= flags; pipe_config 3853 drivers/gpu/drm/i915/display/intel_ddi.c pipe_config->pipe_bpp = 18; pipe_config 3856 drivers/gpu/drm/i915/display/intel_ddi.c pipe_config->pipe_bpp = 24; pipe_config 3859 drivers/gpu/drm/i915/display/intel_ddi.c pipe_config->pipe_bpp = 30; pipe_config 3862 drivers/gpu/drm/i915/display/intel_ddi.c pipe_config->pipe_bpp = 36; pipe_config 3870 drivers/gpu/drm/i915/display/intel_ddi.c pipe_config->has_hdmi_sink = true; pipe_config 3872 drivers/gpu/drm/i915/display/intel_ddi.c pipe_config->infoframes.enable |= pipe_config 3873 drivers/gpu/drm/i915/display/intel_ddi.c intel_hdmi_infoframes_enabled(encoder, pipe_config); pipe_config 3875 drivers/gpu/drm/i915/display/intel_ddi.c if (pipe_config->infoframes.enable) pipe_config 3876 drivers/gpu/drm/i915/display/intel_ddi.c pipe_config->has_infoframe = true; pipe_config 3879 drivers/gpu/drm/i915/display/intel_ddi.c pipe_config->hdmi_scrambling = true; pipe_config 3881 drivers/gpu/drm/i915/display/intel_ddi.c pipe_config->hdmi_high_tmds_clock_ratio = true; pipe_config 3884 drivers/gpu/drm/i915/display/intel_ddi.c pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); pipe_config 3885 drivers/gpu/drm/i915/display/intel_ddi.c pipe_config->lane_count = 4; pipe_config 3888 drivers/gpu/drm/i915/display/intel_ddi.c pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); pipe_config 3892 drivers/gpu/drm/i915/display/intel_ddi.c pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP); pipe_config 3894 drivers/gpu/drm/i915/display/intel_ddi.c pipe_config->output_types |= BIT(INTEL_OUTPUT_DP); pipe_config 3895 drivers/gpu/drm/i915/display/intel_ddi.c pipe_config->lane_count = pipe_config 3897 drivers/gpu/drm/i915/display/intel_ddi.c intel_dp_get_m_n(intel_crtc, pipe_config); pipe_config 3900 drivers/gpu/drm/i915/display/intel_ddi.c pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST); pipe_config 3901 drivers/gpu/drm/i915/display/intel_ddi.c pipe_config->lane_count = pipe_config 3903 drivers/gpu/drm/i915/display/intel_ddi.c intel_dp_get_m_n(intel_crtc, pipe_config); pipe_config 3909 drivers/gpu/drm/i915/display/intel_ddi.c pipe_config->has_audio = pipe_config 3913 drivers/gpu/drm/i915/display/intel_ddi.c pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { pipe_config 3928 drivers/gpu/drm/i915/display/intel_ddi.c pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); pipe_config 3929 drivers/gpu/drm/i915/display/intel_ddi.c dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp; pipe_config 3932 drivers/gpu/drm/i915/display/intel_ddi.c intel_ddi_clock_get(encoder, pipe_config); pipe_config 3935 drivers/gpu/drm/i915/display/intel_ddi.c pipe_config->lane_lat_optim_mask = pipe_config 3938 drivers/gpu/drm/i915/display/intel_ddi.c intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); pipe_config 3940 drivers/gpu/drm/i915/display/intel_ddi.c intel_hdmi_read_gcp_infoframe(encoder, pipe_config); pipe_config 3942 drivers/gpu/drm/i915/display/intel_ddi.c intel_read_infoframe(encoder, pipe_config, pipe_config 3944 drivers/gpu/drm/i915/display/intel_ddi.c &pipe_config->infoframes.avi); pipe_config 3945 drivers/gpu/drm/i915/display/intel_ddi.c intel_read_infoframe(encoder, pipe_config, pipe_config 3947 drivers/gpu/drm/i915/display/intel_ddi.c &pipe_config->infoframes.spd); pipe_config 3948 drivers/gpu/drm/i915/display/intel_ddi.c intel_read_infoframe(encoder, pipe_config, pipe_config 3950 drivers/gpu/drm/i915/display/intel_ddi.c &pipe_config->infoframes.hdmi); pipe_config 3951 drivers/gpu/drm/i915/display/intel_ddi.c intel_read_infoframe(encoder, pipe_config, pipe_config 3953 drivers/gpu/drm/i915/display/intel_ddi.c &pipe_config->infoframes.drm); pipe_config 3975 drivers/gpu/drm/i915/display/intel_ddi.c struct intel_crtc_state *pipe_config, pipe_config 3978 drivers/gpu/drm/i915/display/intel_ddi.c struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); pipe_config 3984 drivers/gpu/drm/i915/display/intel_ddi.c pipe_config->cpu_transcoder = TRANSCODER_EDP; pipe_config 3986 drivers/gpu/drm/i915/display/intel_ddi.c if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) pipe_config 3987 drivers/gpu/drm/i915/display/intel_ddi.c ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state); pipe_config 3989 drivers/gpu/drm/i915/display/intel_ddi.c ret = intel_dp_compute_config(encoder, pipe_config, conn_state); pipe_config 3994 drivers/gpu/drm/i915/display/intel_ddi.c pipe_config->cpu_transcoder == TRANSCODER_EDP) pipe_config 3995 drivers/gpu/drm/i915/display/intel_ddi.c pipe_config->pch_pfit.force_thru = pipe_config 3996 drivers/gpu/drm/i915/display/intel_ddi.c pipe_config->pch_pfit.enabled || pipe_config 3997 drivers/gpu/drm/i915/display/intel_ddi.c pipe_config->crc_enabled; pipe_config 4000 drivers/gpu/drm/i915/display/intel_ddi.c pipe_config->lane_lat_optim_mask = pipe_config 4001 drivers/gpu/drm/i915/display/intel_ddi.c bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); pipe_config 4003 drivers/gpu/drm/i915/display/intel_ddi.c intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); pipe_config 36 drivers/gpu/drm/i915/display/intel_ddi.h struct intel_crtc_state *pipe_config); pipe_config 118 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *pipe_config); pipe_config 120 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *pipe_config); pipe_config 135 drivers/gpu/drm/i915/display/intel_display.c const struct intel_crtc_state *pipe_config); pipe_config 137 drivers/gpu/drm/i915/display/intel_display.c const struct intel_crtc_state *pipe_config); pipe_config 218 drivers/gpu/drm/i915/display/intel_display.c const struct intel_crtc_state *pipe_config) pipe_config 221 drivers/gpu/drm/i915/display/intel_display.c return pipe_config->port_clock; /* SPLL */ pipe_config 1376 drivers/gpu/drm/i915/display/intel_display.c const struct intel_crtc_state *pipe_config) pipe_config 1381 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); pipe_config 1390 drivers/gpu/drm/i915/display/intel_display.c const struct intel_crtc_state *pipe_config) pipe_config 1400 drivers/gpu/drm/i915/display/intel_display.c if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) pipe_config 1401 drivers/gpu/drm/i915/display/intel_display.c _vlv_enable_pll(crtc, pipe_config); pipe_config 1403 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); pipe_config 1409 drivers/gpu/drm/i915/display/intel_display.c const struct intel_crtc_state *pipe_config) pipe_config 1431 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); pipe_config 1439 drivers/gpu/drm/i915/display/intel_display.c const struct intel_crtc_state *pipe_config) pipe_config 1449 drivers/gpu/drm/i915/display/intel_display.c if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) pipe_config 1450 drivers/gpu/drm/i915/display/intel_display.c _chv_enable_pll(crtc, pipe_config); pipe_config 1460 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md); pipe_config 1462 drivers/gpu/drm/i915/display/intel_display.c dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md; pipe_config 1470 drivers/gpu/drm/i915/display/intel_display.c I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); pipe_config 5905 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *pipe_config = pipe_config 5912 drivers/gpu/drm/i915/display/intel_display.c intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits); pipe_config 5914 drivers/gpu/drm/i915/display/intel_display.c if (pipe_config->update_wm_post && pipe_config->base.active) pipe_config 5917 drivers/gpu/drm/i915/display/intel_display.c if (hsw_post_update_enable_ips(old_crtc_state, pipe_config)) pipe_config 5918 drivers/gpu/drm/i915/display/intel_display.c hsw_enable_ips(pipe_config); pipe_config 5927 drivers/gpu/drm/i915/display/intel_display.c (needs_modeset(pipe_config) || pipe_config 5929 drivers/gpu/drm/i915/display/intel_display.c intel_post_enable_primary(&crtc->base, pipe_config); pipe_config 5933 drivers/gpu/drm/i915/display/intel_display.c !needs_nv12_wa(dev_priv, pipe_config)) pipe_config 5937 drivers/gpu/drm/i915/display/intel_display.c !needs_scalerclk_wa(dev_priv, pipe_config)) pipe_config 5942 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *pipe_config) pipe_config 5951 drivers/gpu/drm/i915/display/intel_display.c bool modeset = needs_modeset(pipe_config); pipe_config 5955 drivers/gpu/drm/i915/display/intel_display.c if (hsw_pre_update_disable_ips(old_crtc_state, pipe_config)) pipe_config 5963 drivers/gpu/drm/i915/display/intel_display.c intel_fbc_pre_update(crtc, pipe_config, new_primary_state); pipe_config 5975 drivers/gpu/drm/i915/display/intel_display.c needs_nv12_wa(dev_priv, pipe_config)) pipe_config 5980 drivers/gpu/drm/i915/display/intel_display.c needs_scalerclk_wa(dev_priv, pipe_config)) pipe_config 5993 drivers/gpu/drm/i915/display/intel_display.c pipe_config->disable_cxsr && intel_set_memory_cxsr(dev_priv, false)) pipe_config 6003 drivers/gpu/drm/i915/display/intel_display.c if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev) && pipe_config 6011 drivers/gpu/drm/i915/display/intel_display.c if (needs_modeset(pipe_config)) pipe_config 6030 drivers/gpu/drm/i915/display/intel_display.c pipe_config); pipe_config 6031 drivers/gpu/drm/i915/display/intel_display.c else if (pipe_config->update_wm_pre) pipe_config 6305 drivers/gpu/drm/i915/display/intel_display.c static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config, pipe_config 6308 drivers/gpu/drm/i915/display/intel_display.c struct drm_crtc *crtc = pipe_config->base.crtc; pipe_config 6330 drivers/gpu/drm/i915/display/intel_display.c if (pipe_config->has_pch_encoder) pipe_config 6331 drivers/gpu/drm/i915/display/intel_display.c intel_prepare_shared_dpll(pipe_config); pipe_config 6333 drivers/gpu/drm/i915/display/intel_display.c if (intel_crtc_has_dp_encoder(pipe_config)) pipe_config 6334 drivers/gpu/drm/i915/display/intel_display.c intel_dp_set_m_n(pipe_config, M1_N1); pipe_config 6336 drivers/gpu/drm/i915/display/intel_display.c intel_set_pipe_timings(pipe_config); pipe_config 6337 drivers/gpu/drm/i915/display/intel_display.c intel_set_pipe_src_size(pipe_config); pipe_config 6339 drivers/gpu/drm/i915/display/intel_display.c if (pipe_config->has_pch_encoder) { pipe_config 6340 drivers/gpu/drm/i915/display/intel_display.c intel_cpu_transcoder_set_m_n(pipe_config, pipe_config 6341 drivers/gpu/drm/i915/display/intel_display.c &pipe_config->fdi_m_n, NULL); pipe_config 6344 drivers/gpu/drm/i915/display/intel_display.c ironlake_set_pipeconf(pipe_config); pipe_config 6348 drivers/gpu/drm/i915/display/intel_display.c intel_encoders_pre_enable(intel_crtc, pipe_config, state); pipe_config 6350 drivers/gpu/drm/i915/display/intel_display.c if (pipe_config->has_pch_encoder) { pipe_config 6354 drivers/gpu/drm/i915/display/intel_display.c ironlake_fdi_pll_enable(pipe_config); pipe_config 6360 drivers/gpu/drm/i915/display/intel_display.c ironlake_pfit_enable(pipe_config); pipe_config 6366 drivers/gpu/drm/i915/display/intel_display.c intel_color_load_luts(pipe_config); pipe_config 6367 drivers/gpu/drm/i915/display/intel_display.c intel_color_commit(pipe_config); pipe_config 6369 drivers/gpu/drm/i915/display/intel_display.c intel_disable_primary_plane(pipe_config); pipe_config 6372 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.initial_watermarks(state, pipe_config); pipe_config 6373 drivers/gpu/drm/i915/display/intel_display.c intel_enable_pipe(pipe_config); pipe_config 6375 drivers/gpu/drm/i915/display/intel_display.c if (pipe_config->has_pch_encoder) pipe_config 6376 drivers/gpu/drm/i915/display/intel_display.c ironlake_pch_enable(state, pipe_config); pipe_config 6379 drivers/gpu/drm/i915/display/intel_display.c intel_crtc_vblank_on(pipe_config); pipe_config 6381 drivers/gpu/drm/i915/display/intel_display.c intel_encoders_enable(intel_crtc, pipe_config, state); pipe_config 6392 drivers/gpu/drm/i915/display/intel_display.c if (pipe_config->has_pch_encoder) { pipe_config 6439 drivers/gpu/drm/i915/display/intel_display.c static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, pipe_config 6442 drivers/gpu/drm/i915/display/intel_display.c struct drm_crtc *crtc = pipe_config->base.crtc; pipe_config 6446 drivers/gpu/drm/i915/display/intel_display.c enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; pipe_config 6452 drivers/gpu/drm/i915/display/intel_display.c intel_encoders_pre_pll_enable(intel_crtc, pipe_config, state); pipe_config 6454 drivers/gpu/drm/i915/display/intel_display.c if (pipe_config->shared_dpll) pipe_config 6455 drivers/gpu/drm/i915/display/intel_display.c intel_enable_shared_dpll(pipe_config); pipe_config 6457 drivers/gpu/drm/i915/display/intel_display.c intel_encoders_pre_enable(intel_crtc, pipe_config, state); pipe_config 6459 drivers/gpu/drm/i915/display/intel_display.c if (intel_crtc_has_dp_encoder(pipe_config)) pipe_config 6460 drivers/gpu/drm/i915/display/intel_display.c intel_dp_set_m_n(pipe_config, M1_N1); pipe_config 6463 drivers/gpu/drm/i915/display/intel_display.c intel_set_pipe_timings(pipe_config); pipe_config 6465 drivers/gpu/drm/i915/display/intel_display.c intel_set_pipe_src_size(pipe_config); pipe_config 6470 drivers/gpu/drm/i915/display/intel_display.c pipe_config->pixel_multiplier - 1); pipe_config 6473 drivers/gpu/drm/i915/display/intel_display.c if (pipe_config->has_pch_encoder) { pipe_config 6474 drivers/gpu/drm/i915/display/intel_display.c intel_cpu_transcoder_set_m_n(pipe_config, pipe_config 6475 drivers/gpu/drm/i915/display/intel_display.c &pipe_config->fdi_m_n, NULL); pipe_config 6479 drivers/gpu/drm/i915/display/intel_display.c haswell_set_pipeconf(pipe_config); pipe_config 6482 drivers/gpu/drm/i915/display/intel_display.c bdw_set_pipemisc(pipe_config); pipe_config 6488 drivers/gpu/drm/i915/display/intel_display.c pipe_config->pch_pfit.enabled; pipe_config 6493 drivers/gpu/drm/i915/display/intel_display.c skylake_pfit_enable(pipe_config); pipe_config 6495 drivers/gpu/drm/i915/display/intel_display.c ironlake_pfit_enable(pipe_config); pipe_config 6501 drivers/gpu/drm/i915/display/intel_display.c intel_color_load_luts(pipe_config); pipe_config 6502 drivers/gpu/drm/i915/display/intel_display.c intel_color_commit(pipe_config); pipe_config 6505 drivers/gpu/drm/i915/display/intel_display.c intel_disable_primary_plane(pipe_config); pipe_config 6510 drivers/gpu/drm/i915/display/intel_display.c intel_ddi_set_pipe_settings(pipe_config); pipe_config 6512 drivers/gpu/drm/i915/display/intel_display.c intel_ddi_enable_transcoder_func(pipe_config); pipe_config 6515 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.initial_watermarks(state, pipe_config); pipe_config 6522 drivers/gpu/drm/i915/display/intel_display.c intel_enable_pipe(pipe_config); pipe_config 6524 drivers/gpu/drm/i915/display/intel_display.c if (pipe_config->has_pch_encoder) pipe_config 6525 drivers/gpu/drm/i915/display/intel_display.c lpt_pch_enable(state, pipe_config); pipe_config 6527 drivers/gpu/drm/i915/display/intel_display.c if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST)) pipe_config 6528 drivers/gpu/drm/i915/display/intel_display.c intel_ddi_set_vc_payload_alloc(pipe_config, true); pipe_config 6531 drivers/gpu/drm/i915/display/intel_display.c intel_crtc_vblank_on(pipe_config); pipe_config 6533 drivers/gpu/drm/i915/display/intel_display.c intel_encoders_enable(intel_crtc, pipe_config, state); pipe_config 6542 drivers/gpu/drm/i915/display/intel_display.c hsw_workaround_pipe = pipe_config->hsw_workaround_pipe; pipe_config 6851 drivers/gpu/drm/i915/display/intel_display.c static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config, pipe_config 6854 drivers/gpu/drm/i915/display/intel_display.c struct drm_crtc *crtc = pipe_config->base.crtc; pipe_config 6863 drivers/gpu/drm/i915/display/intel_display.c if (intel_crtc_has_dp_encoder(pipe_config)) pipe_config 6864 drivers/gpu/drm/i915/display/intel_display.c intel_dp_set_m_n(pipe_config, M1_N1); pipe_config 6866 drivers/gpu/drm/i915/display/intel_display.c intel_set_pipe_timings(pipe_config); pipe_config 6867 drivers/gpu/drm/i915/display/intel_display.c intel_set_pipe_src_size(pipe_config); pipe_config 6874 drivers/gpu/drm/i915/display/intel_display.c i9xx_set_pipeconf(pipe_config); pipe_config 6880 drivers/gpu/drm/i915/display/intel_display.c intel_encoders_pre_pll_enable(intel_crtc, pipe_config, state); pipe_config 6883 drivers/gpu/drm/i915/display/intel_display.c chv_prepare_pll(intel_crtc, pipe_config); pipe_config 6884 drivers/gpu/drm/i915/display/intel_display.c chv_enable_pll(intel_crtc, pipe_config); pipe_config 6886 drivers/gpu/drm/i915/display/intel_display.c vlv_prepare_pll(intel_crtc, pipe_config); pipe_config 6887 drivers/gpu/drm/i915/display/intel_display.c vlv_enable_pll(intel_crtc, pipe_config); pipe_config 6890 drivers/gpu/drm/i915/display/intel_display.c intel_encoders_pre_enable(intel_crtc, pipe_config, state); pipe_config 6892 drivers/gpu/drm/i915/display/intel_display.c i9xx_pfit_enable(pipe_config); pipe_config 6894 drivers/gpu/drm/i915/display/intel_display.c intel_color_load_luts(pipe_config); pipe_config 6895 drivers/gpu/drm/i915/display/intel_display.c intel_color_commit(pipe_config); pipe_config 6897 drivers/gpu/drm/i915/display/intel_display.c intel_disable_primary_plane(pipe_config); pipe_config 6899 drivers/gpu/drm/i915/display/intel_display.c dev_priv->display.initial_watermarks(state, pipe_config); pipe_config 6900 drivers/gpu/drm/i915/display/intel_display.c intel_enable_pipe(pipe_config); pipe_config 6903 drivers/gpu/drm/i915/display/intel_display.c intel_crtc_vblank_on(pipe_config); pipe_config 6905 drivers/gpu/drm/i915/display/intel_display.c intel_encoders_enable(intel_crtc, pipe_config, state); pipe_config 6917 drivers/gpu/drm/i915/display/intel_display.c static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config, pipe_config 6920 drivers/gpu/drm/i915/display/intel_display.c struct drm_crtc *crtc = pipe_config->base.crtc; pipe_config 6929 drivers/gpu/drm/i915/display/intel_display.c i9xx_set_pll_dividers(pipe_config); pipe_config 6931 drivers/gpu/drm/i915/display/intel_display.c if (intel_crtc_has_dp_encoder(pipe_config)) pipe_config 6932 drivers/gpu/drm/i915/display/intel_display.c intel_dp_set_m_n(pipe_config, M1_N1); pipe_config 6934 drivers/gpu/drm/i915/display/intel_display.c intel_set_pipe_timings(pipe_config); pipe_config 6935 drivers/gpu/drm/i915/display/intel_display.c intel_set_pipe_src_size(pipe_config); pipe_config 6937 drivers/gpu/drm/i915/display/intel_display.c i9xx_set_pipeconf(pipe_config); pipe_config 6944 drivers/gpu/drm/i915/display/intel_display.c intel_encoders_pre_enable(intel_crtc, pipe_config, state); pipe_config 6946 drivers/gpu/drm/i915/display/intel_display.c i9xx_enable_pll(intel_crtc, pipe_config); pipe_config 6948 drivers/gpu/drm/i915/display/intel_display.c i9xx_pfit_enable(pipe_config); pipe_config 6950 drivers/gpu/drm/i915/display/intel_display.c intel_color_load_luts(pipe_config); pipe_config 6951 drivers/gpu/drm/i915/display/intel_display.c intel_color_commit(pipe_config); pipe_config 6953 drivers/gpu/drm/i915/display/intel_display.c intel_disable_primary_plane(pipe_config); pipe_config 6957 drivers/gpu/drm/i915/display/intel_display.c pipe_config); pipe_config 6960 drivers/gpu/drm/i915/display/intel_display.c intel_enable_pipe(pipe_config); pipe_config 6963 drivers/gpu/drm/i915/display/intel_display.c intel_crtc_vblank_on(pipe_config); pipe_config 6965 drivers/gpu/drm/i915/display/intel_display.c intel_encoders_enable(intel_crtc, pipe_config, state); pipe_config 7182 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *pipe_config) pipe_config 7185 drivers/gpu/drm/i915/display/intel_display.c struct drm_atomic_state *state = pipe_config->base.state; pipe_config 7190 drivers/gpu/drm/i915/display/intel_display.c pipe_name(pipe), pipe_config->fdi_lanes); pipe_config 7191 drivers/gpu/drm/i915/display/intel_display.c if (pipe_config->fdi_lanes > 4) { pipe_config 7193 drivers/gpu/drm/i915/display/intel_display.c pipe_name(pipe), pipe_config->fdi_lanes); pipe_config 7198 drivers/gpu/drm/i915/display/intel_display.c if (pipe_config->fdi_lanes > 2) { pipe_config 7200 drivers/gpu/drm/i915/display/intel_display.c pipe_config->fdi_lanes); pipe_config 7215 drivers/gpu/drm/i915/display/intel_display.c if (pipe_config->fdi_lanes <= 2) pipe_config 7226 drivers/gpu/drm/i915/display/intel_display.c pipe_name(pipe), pipe_config->fdi_lanes); pipe_config 7231 drivers/gpu/drm/i915/display/intel_display.c if (pipe_config->fdi_lanes > 2) { pipe_config 7233 drivers/gpu/drm/i915/display/intel_display.c pipe_name(pipe), pipe_config->fdi_lanes); pipe_config 7255 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *pipe_config) pipe_config 7258 drivers/gpu/drm/i915/display/intel_display.c const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; pipe_config 7270 drivers/gpu/drm/i915/display/intel_display.c link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config); pipe_config 7275 drivers/gpu/drm/i915/display/intel_display.c pipe_config->pipe_bpp); pipe_config 7277 drivers/gpu/drm/i915/display/intel_display.c pipe_config->fdi_lanes = lane; pipe_config 7279 drivers/gpu/drm/i915/display/intel_display.c intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, pipe_config 7280 drivers/gpu/drm/i915/display/intel_display.c link_bw, &pipe_config->fdi_m_n, false, false); pipe_config 7282 drivers/gpu/drm/i915/display/intel_display.c ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config); pipe_config 7286 drivers/gpu/drm/i915/display/intel_display.c if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { pipe_config 7287 drivers/gpu/drm/i915/display/intel_display.c pipe_config->pipe_bpp -= 2*3; pipe_config 7289 drivers/gpu/drm/i915/display/intel_display.c pipe_config->pipe_bpp); pipe_config 7291 drivers/gpu/drm/i915/display/intel_display.c pipe_config->bw_constrained = true; pipe_config 7371 drivers/gpu/drm/i915/display/intel_display.c static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config) pipe_config 7375 drivers/gpu/drm/i915/display/intel_display.c pixel_rate = pipe_config->base.adjusted_mode.crtc_clock; pipe_config 7382 drivers/gpu/drm/i915/display/intel_display.c if (pipe_config->pch_pfit.enabled) { pipe_config 7384 drivers/gpu/drm/i915/display/intel_display.c u32 pfit_size = pipe_config->pch_pfit.size; pipe_config 7386 drivers/gpu/drm/i915/display/intel_display.c pipe_w = pipe_config->pipe_src_w; pipe_config 7387 drivers/gpu/drm/i915/display/intel_display.c pipe_h = pipe_config->pipe_src_h; pipe_config 7420 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *pipe_config) pipe_config 7423 drivers/gpu/drm/i915/display/intel_display.c const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; pipe_config 7436 drivers/gpu/drm/i915/display/intel_display.c pipe_config->double_wide = true; pipe_config 7443 drivers/gpu/drm/i915/display/intel_display.c yesno(pipe_config->double_wide)); pipe_config 7447 drivers/gpu/drm/i915/display/intel_display.c if ((pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 || pipe_config 7448 drivers/gpu/drm/i915/display/intel_display.c pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) && pipe_config 7449 drivers/gpu/drm/i915/display/intel_display.c pipe_config->base.ctm) { pipe_config 7465 drivers/gpu/drm/i915/display/intel_display.c if (pipe_config->pipe_src_w & 1) { pipe_config 7466 drivers/gpu/drm/i915/display/intel_display.c if (pipe_config->double_wide) { pipe_config 7471 drivers/gpu/drm/i915/display/intel_display.c if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) && pipe_config 7485 drivers/gpu/drm/i915/display/intel_display.c intel_crtc_compute_pixel_rate(pipe_config); pipe_config 7487 drivers/gpu/drm/i915/display/intel_display.c if (pipe_config->has_pch_encoder) pipe_config 7488 drivers/gpu/drm/i915/display/intel_display.c return ironlake_fdi_compute_config(crtc, pipe_config); pipe_config 7705 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *pipe_config) pipe_config 7707 drivers/gpu/drm/i915/display/intel_display.c pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV | pipe_config 7710 drivers/gpu/drm/i915/display/intel_display.c pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; pipe_config 7713 drivers/gpu/drm/i915/display/intel_display.c if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI)) pipe_config 7714 drivers/gpu/drm/i915/display/intel_display.c pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE | pipe_config 7717 drivers/gpu/drm/i915/display/intel_display.c pipe_config->dpll_hw_state.dpll_md = pipe_config 7718 drivers/gpu/drm/i915/display/intel_display.c (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; pipe_config 7722 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *pipe_config) pipe_config 7724 drivers/gpu/drm/i915/display/intel_display.c pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | pipe_config 7727 drivers/gpu/drm/i915/display/intel_display.c pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; pipe_config 7730 drivers/gpu/drm/i915/display/intel_display.c if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI)) pipe_config 7731 drivers/gpu/drm/i915/display/intel_display.c pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE; pipe_config 7733 drivers/gpu/drm/i915/display/intel_display.c pipe_config->dpll_hw_state.dpll_md = pipe_config 7734 drivers/gpu/drm/i915/display/intel_display.c (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; pipe_config 7738 drivers/gpu/drm/i915/display/intel_display.c const struct intel_crtc_state *pipe_config) pipe_config 7749 drivers/gpu/drm/i915/display/intel_display.c pipe_config->dpll_hw_state.dpll & pipe_config 7753 drivers/gpu/drm/i915/display/intel_display.c if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) pipe_config 7758 drivers/gpu/drm/i915/display/intel_display.c bestn = pipe_config->dpll.n; pipe_config 7759 drivers/gpu/drm/i915/display/intel_display.c bestm1 = pipe_config->dpll.m1; pipe_config 7760 drivers/gpu/drm/i915/display/intel_display.c bestm2 = pipe_config->dpll.m2; pipe_config 7761 drivers/gpu/drm/i915/display/intel_display.c bestp1 = pipe_config->dpll.p1; pipe_config 7762 drivers/gpu/drm/i915/display/intel_display.c bestp2 = pipe_config->dpll.p2; pipe_config 7799 drivers/gpu/drm/i915/display/intel_display.c if (pipe_config->port_clock == 162000 || pipe_config 7800 drivers/gpu/drm/i915/display/intel_display.c intel_crtc_has_type(pipe_config, INTEL_OUTPUT_ANALOG) || pipe_config 7801 drivers/gpu/drm/i915/display/intel_display.c intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) pipe_config 7808 drivers/gpu/drm/i915/display/intel_display.c if (intel_crtc_has_dp_encoder(pipe_config)) { pipe_config 7828 drivers/gpu/drm/i915/display/intel_display.c if (intel_crtc_has_dp_encoder(pipe_config)) pipe_config 7838 drivers/gpu/drm/i915/display/intel_display.c const struct intel_crtc_state *pipe_config) pipe_config 7851 drivers/gpu/drm/i915/display/intel_display.c pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); pipe_config 7854 drivers/gpu/drm/i915/display/intel_display.c if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) pipe_config 7857 drivers/gpu/drm/i915/display/intel_display.c bestn = pipe_config->dpll.n; pipe_config 7858 drivers/gpu/drm/i915/display/intel_display.c bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; pipe_config 7859 drivers/gpu/drm/i915/display/intel_display.c bestm1 = pipe_config->dpll.m1; pipe_config 7860 drivers/gpu/drm/i915/display/intel_display.c bestm2 = pipe_config->dpll.m2 >> 22; pipe_config 7861 drivers/gpu/drm/i915/display/intel_display.c bestp1 = pipe_config->dpll.p1; pipe_config 7862 drivers/gpu/drm/i915/display/intel_display.c bestp2 = pipe_config->dpll.p2; pipe_config 7863 drivers/gpu/drm/i915/display/intel_display.c vco = pipe_config->dpll.vco; pipe_config 7956 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *pipe_config; pipe_config 7958 drivers/gpu/drm/i915/display/intel_display.c pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); pipe_config 7959 drivers/gpu/drm/i915/display/intel_display.c if (!pipe_config) pipe_config 7962 drivers/gpu/drm/i915/display/intel_display.c pipe_config->base.crtc = &crtc->base; pipe_config 7963 drivers/gpu/drm/i915/display/intel_display.c pipe_config->pixel_multiplier = 1; pipe_config 7964 drivers/gpu/drm/i915/display/intel_display.c pipe_config->dpll = *dpll; pipe_config 7967 drivers/gpu/drm/i915/display/intel_display.c chv_compute_dpll(crtc, pipe_config); pipe_config 7968 drivers/gpu/drm/i915/display/intel_display.c chv_prepare_pll(crtc, pipe_config); pipe_config 7969 drivers/gpu/drm/i915/display/intel_display.c chv_enable_pll(crtc, pipe_config); pipe_config 7971 drivers/gpu/drm/i915/display/intel_display.c vlv_compute_dpll(crtc, pipe_config); pipe_config 7972 drivers/gpu/drm/i915/display/intel_display.c vlv_prepare_pll(crtc, pipe_config); pipe_config 7973 drivers/gpu/drm/i915/display/intel_display.c vlv_enable_pll(crtc, pipe_config); pipe_config 7976 drivers/gpu/drm/i915/display/intel_display.c kfree(pipe_config); pipe_config 8197 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *pipe_config) pipe_config 8201 drivers/gpu/drm/i915/display/intel_display.c enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; pipe_config 8205 drivers/gpu/drm/i915/display/intel_display.c pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; pipe_config 8206 drivers/gpu/drm/i915/display/intel_display.c pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; pipe_config 8210 drivers/gpu/drm/i915/display/intel_display.c pipe_config->base.adjusted_mode.crtc_hblank_start = pipe_config 8212 drivers/gpu/drm/i915/display/intel_display.c pipe_config->base.adjusted_mode.crtc_hblank_end = pipe_config 8216 drivers/gpu/drm/i915/display/intel_display.c pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; pipe_config 8217 drivers/gpu/drm/i915/display/intel_display.c pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; pipe_config 8220 drivers/gpu/drm/i915/display/intel_display.c pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; pipe_config 8221 drivers/gpu/drm/i915/display/intel_display.c pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; pipe_config 8225 drivers/gpu/drm/i915/display/intel_display.c pipe_config->base.adjusted_mode.crtc_vblank_start = pipe_config 8227 drivers/gpu/drm/i915/display/intel_display.c pipe_config->base.adjusted_mode.crtc_vblank_end = pipe_config 8231 drivers/gpu/drm/i915/display/intel_display.c pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; pipe_config 8232 drivers/gpu/drm/i915/display/intel_display.c pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; pipe_config 8235 drivers/gpu/drm/i915/display/intel_display.c pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; pipe_config 8236 drivers/gpu/drm/i915/display/intel_display.c pipe_config->base.adjusted_mode.crtc_vtotal += 1; pipe_config 8237 drivers/gpu/drm/i915/display/intel_display.c pipe_config->base.adjusted_mode.crtc_vblank_end += 1; pipe_config 8242 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *pipe_config) pipe_config 8249 drivers/gpu/drm/i915/display/intel_display.c pipe_config->pipe_src_h = (tmp & 0xffff) + 1; pipe_config 8250 drivers/gpu/drm/i915/display/intel_display.c pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; pipe_config 8252 drivers/gpu/drm/i915/display/intel_display.c pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; pipe_config 8253 drivers/gpu/drm/i915/display/intel_display.c pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; pipe_config 8257 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *pipe_config) pipe_config 8259 drivers/gpu/drm/i915/display/intel_display.c mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; pipe_config 8260 drivers/gpu/drm/i915/display/intel_display.c mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; pipe_config 8261 drivers/gpu/drm/i915/display/intel_display.c mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; pipe_config 8262 drivers/gpu/drm/i915/display/intel_display.c mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; pipe_config 8264 drivers/gpu/drm/i915/display/intel_display.c mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; pipe_config 8265 drivers/gpu/drm/i915/display/intel_display.c mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; pipe_config 8266 drivers/gpu/drm/i915/display/intel_display.c mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; pipe_config 8267 drivers/gpu/drm/i915/display/intel_display.c mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; pipe_config 8269 drivers/gpu/drm/i915/display/intel_display.c mode->flags = pipe_config->base.adjusted_mode.flags; pipe_config 8272 drivers/gpu/drm/i915/display/intel_display.c mode->clock = pipe_config->base.adjusted_mode.crtc_clock; pipe_config 8536 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *pipe_config) pipe_config 8557 drivers/gpu/drm/i915/display/intel_display.c pipe_config->gmch_pfit.control = tmp; pipe_config 8558 drivers/gpu/drm/i915/display/intel_display.c pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); pipe_config 8562 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *pipe_config) pipe_config 8566 drivers/gpu/drm/i915/display/intel_display.c int pipe = pipe_config->cpu_transcoder; pipe_config 8572 drivers/gpu/drm/i915/display/intel_display.c if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) pipe_config 8585 drivers/gpu/drm/i915/display/intel_display.c pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); pipe_config 8672 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *pipe_config) pipe_config 8676 drivers/gpu/drm/i915/display/intel_display.c int pipe = pipe_config->cpu_transcoder; pipe_config 8683 drivers/gpu/drm/i915/display/intel_display.c if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) pipe_config 8702 drivers/gpu/drm/i915/display/intel_display.c pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); pipe_config 8706 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *pipe_config) pipe_config 8711 drivers/gpu/drm/i915/display/intel_display.c pipe_config->lspcon_downsampling = false; pipe_config 8739 drivers/gpu/drm/i915/display/intel_display.c pipe_config->lspcon_downsampling = true; pipe_config 8745 drivers/gpu/drm/i915/display/intel_display.c pipe_config->output_format = output; pipe_config 8767 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *pipe_config) pipe_config 8780 drivers/gpu/drm/i915/display/intel_display.c pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; pipe_config 8781 drivers/gpu/drm/i915/display/intel_display.c pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; pipe_config 8782 drivers/gpu/drm/i915/display/intel_display.c pipe_config->shared_dpll = NULL; pipe_config 8794 drivers/gpu/drm/i915/display/intel_display.c pipe_config->pipe_bpp = 18; pipe_config 8797 drivers/gpu/drm/i915/display/intel_display.c pipe_config->pipe_bpp = 24; pipe_config 8800 drivers/gpu/drm/i915/display/intel_display.c pipe_config->pipe_bpp = 30; pipe_config 8809 drivers/gpu/drm/i915/display/intel_display.c pipe_config->limited_color_range = true; pipe_config 8811 drivers/gpu/drm/i915/display/intel_display.c pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_I9XX) >> pipe_config 8815 drivers/gpu/drm/i915/display/intel_display.c pipe_config->cgm_mode = I915_READ(CGM_PIPE_MODE(crtc->pipe)); pipe_config 8817 drivers/gpu/drm/i915/display/intel_display.c i9xx_get_pipe_color_config(pipe_config); pipe_config 8818 drivers/gpu/drm/i915/display/intel_display.c intel_color_get_config(pipe_config); pipe_config 8821 drivers/gpu/drm/i915/display/intel_display.c pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; pipe_config 8823 drivers/gpu/drm/i915/display/intel_display.c intel_get_pipe_timings(crtc, pipe_config); pipe_config 8824 drivers/gpu/drm/i915/display/intel_display.c intel_get_pipe_src_size(crtc, pipe_config); pipe_config 8826 drivers/gpu/drm/i915/display/intel_display.c i9xx_get_pfit_config(crtc, pipe_config); pipe_config 8834 drivers/gpu/drm/i915/display/intel_display.c pipe_config->pixel_multiplier = pipe_config 8837 drivers/gpu/drm/i915/display/intel_display.c pipe_config->dpll_hw_state.dpll_md = tmp; pipe_config 8841 drivers/gpu/drm/i915/display/intel_display.c pipe_config->pixel_multiplier = pipe_config 8848 drivers/gpu/drm/i915/display/intel_display.c pipe_config->pixel_multiplier = 1; pipe_config 8850 drivers/gpu/drm/i915/display/intel_display.c pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); pipe_config 8852 drivers/gpu/drm/i915/display/intel_display.c pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); pipe_config 8853 drivers/gpu/drm/i915/display/intel_display.c pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); pipe_config 8856 drivers/gpu/drm/i915/display/intel_display.c pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | pipe_config 8862 drivers/gpu/drm/i915/display/intel_display.c chv_crtc_clock_get(crtc, pipe_config); pipe_config 8864 drivers/gpu/drm/i915/display/intel_display.c vlv_crtc_clock_get(crtc, pipe_config); pipe_config 8866 drivers/gpu/drm/i915/display/intel_display.c i9xx_crtc_clock_get(crtc, pipe_config); pipe_config 8873 drivers/gpu/drm/i915/display/intel_display.c pipe_config->base.adjusted_mode.crtc_clock = pipe_config 8874 drivers/gpu/drm/i915/display/intel_display.c pipe_config->port_clock / pipe_config->pixel_multiplier; pipe_config 9743 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *pipe_config) pipe_config 9745 drivers/gpu/drm/i915/display/intel_display.c if (pipe_config->has_pch_encoder) pipe_config 9746 drivers/gpu/drm/i915/display/intel_display.c intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); pipe_config 9748 drivers/gpu/drm/i915/display/intel_display.c intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, pipe_config 9749 drivers/gpu/drm/i915/display/intel_display.c &pipe_config->dp_m_n, pipe_config 9750 drivers/gpu/drm/i915/display/intel_display.c &pipe_config->dp_m2_n2); pipe_config 9754 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *pipe_config) pipe_config 9756 drivers/gpu/drm/i915/display/intel_display.c intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, pipe_config 9757 drivers/gpu/drm/i915/display/intel_display.c &pipe_config->fdi_m_n, NULL); pipe_config 9761 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *pipe_config) pipe_config 9765 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state; pipe_config 9775 drivers/gpu/drm/i915/display/intel_display.c pipe_config->pch_pfit.enabled = true; pipe_config 9776 drivers/gpu/drm/i915/display/intel_display.c pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)); pipe_config 9777 drivers/gpu/drm/i915/display/intel_display.c pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)); pipe_config 9919 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *pipe_config) pipe_config 9928 drivers/gpu/drm/i915/display/intel_display.c pipe_config->pch_pfit.enabled = true; pipe_config 9929 drivers/gpu/drm/i915/display/intel_display.c pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); pipe_config 9930 drivers/gpu/drm/i915/display/intel_display.c pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); pipe_config 9943 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *pipe_config) pipe_config 9957 drivers/gpu/drm/i915/display/intel_display.c pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; pipe_config 9958 drivers/gpu/drm/i915/display/intel_display.c pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; pipe_config 9959 drivers/gpu/drm/i915/display/intel_display.c pipe_config->shared_dpll = NULL; pipe_config 9968 drivers/gpu/drm/i915/display/intel_display.c pipe_config->pipe_bpp = 18; pipe_config 9971 drivers/gpu/drm/i915/display/intel_display.c pipe_config->pipe_bpp = 24; pipe_config 9974 drivers/gpu/drm/i915/display/intel_display.c pipe_config->pipe_bpp = 30; pipe_config 9977 drivers/gpu/drm/i915/display/intel_display.c pipe_config->pipe_bpp = 36; pipe_config 9984 drivers/gpu/drm/i915/display/intel_display.c pipe_config->limited_color_range = true; pipe_config 9986 drivers/gpu/drm/i915/display/intel_display.c pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_ILK) >> pipe_config 9989 drivers/gpu/drm/i915/display/intel_display.c pipe_config->csc_mode = I915_READ(PIPE_CSC_MODE(crtc->pipe)); pipe_config 9991 drivers/gpu/drm/i915/display/intel_display.c i9xx_get_pipe_color_config(pipe_config); pipe_config 9992 drivers/gpu/drm/i915/display/intel_display.c intel_color_get_config(pipe_config); pipe_config 9998 drivers/gpu/drm/i915/display/intel_display.c pipe_config->has_pch_encoder = true; pipe_config 10001 drivers/gpu/drm/i915/display/intel_display.c pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> pipe_config 10004 drivers/gpu/drm/i915/display/intel_display.c ironlake_get_fdi_m_n_config(crtc, pipe_config); pipe_config 10020 drivers/gpu/drm/i915/display/intel_display.c pipe_config->shared_dpll = pipe_config 10022 drivers/gpu/drm/i915/display/intel_display.c pll = pipe_config->shared_dpll; pipe_config 10025 drivers/gpu/drm/i915/display/intel_display.c &pipe_config->dpll_hw_state)); pipe_config 10027 drivers/gpu/drm/i915/display/intel_display.c tmp = pipe_config->dpll_hw_state.dpll; pipe_config 10028 drivers/gpu/drm/i915/display/intel_display.c pipe_config->pixel_multiplier = pipe_config 10032 drivers/gpu/drm/i915/display/intel_display.c ironlake_pch_clock_get(crtc, pipe_config); pipe_config 10034 drivers/gpu/drm/i915/display/intel_display.c pipe_config->pixel_multiplier = 1; pipe_config 10037 drivers/gpu/drm/i915/display/intel_display.c intel_get_pipe_timings(crtc, pipe_config); pipe_config 10038 drivers/gpu/drm/i915/display/intel_display.c intel_get_pipe_src_size(crtc, pipe_config); pipe_config 10040 drivers/gpu/drm/i915/display/intel_display.c ironlake_get_pfit_config(crtc, pipe_config); pipe_config 10073 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *pipe_config) pipe_config 10084 drivers/gpu/drm/i915/display/intel_display.c pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); pipe_config 10089 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *pipe_config) pipe_config 10118 drivers/gpu/drm/i915/display/intel_display.c pipe_config->icl_port_dplls[port_dpll_id].pll = pipe_config 10121 drivers/gpu/drm/i915/display/intel_display.c icl_set_active_port_dpll(pipe_config, port_dpll_id); pipe_config 10126 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *pipe_config) pipe_config 10145 drivers/gpu/drm/i915/display/intel_display.c pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); pipe_config 10150 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *pipe_config) pipe_config 10161 drivers/gpu/drm/i915/display/intel_display.c pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); pipe_config 10166 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *pipe_config) pipe_config 10197 drivers/gpu/drm/i915/display/intel_display.c pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); pipe_config 10201 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *pipe_config, pipe_config 10225 drivers/gpu/drm/i915/display/intel_display.c pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; pipe_config 10270 drivers/gpu/drm/i915/display/intel_display.c pipe_config->cpu_transcoder = panel_transcoder; pipe_config 10271 drivers/gpu/drm/i915/display/intel_display.c pipe_config->pch_pfit.force_thru = force_thru; pipe_config 10281 drivers/gpu/drm/i915/display/intel_display.c power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder); pipe_config 10291 drivers/gpu/drm/i915/display/intel_display.c tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); pipe_config 10297 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *pipe_config, pipe_config 10344 drivers/gpu/drm/i915/display/intel_display.c pipe_config->cpu_transcoder = cpu_transcoder; pipe_config 10348 drivers/gpu/drm/i915/display/intel_display.c return transcoder_is_dsi(pipe_config->cpu_transcoder); pipe_config 10352 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *pipe_config) pipe_config 10359 drivers/gpu/drm/i915/display/intel_display.c tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); pipe_config 10367 drivers/gpu/drm/i915/display/intel_display.c icelake_get_ddi_pll(dev_priv, port, pipe_config); pipe_config 10369 drivers/gpu/drm/i915/display/intel_display.c cannonlake_get_ddi_pll(dev_priv, port, pipe_config); pipe_config 10371 drivers/gpu/drm/i915/display/intel_display.c skylake_get_ddi_pll(dev_priv, port, pipe_config); pipe_config 10373 drivers/gpu/drm/i915/display/intel_display.c bxt_get_ddi_pll(dev_priv, port, pipe_config); pipe_config 10375 drivers/gpu/drm/i915/display/intel_display.c haswell_get_ddi_pll(dev_priv, port, pipe_config); pipe_config 10377 drivers/gpu/drm/i915/display/intel_display.c pll = pipe_config->shared_dpll; pipe_config 10380 drivers/gpu/drm/i915/display/intel_display.c &pipe_config->dpll_hw_state)); pipe_config 10390 drivers/gpu/drm/i915/display/intel_display.c pipe_config->has_pch_encoder = true; pipe_config 10393 drivers/gpu/drm/i915/display/intel_display.c pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> pipe_config 10396 drivers/gpu/drm/i915/display/intel_display.c ironlake_get_fdi_m_n_config(crtc, pipe_config); pipe_config 10401 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *pipe_config) pipe_config 10409 drivers/gpu/drm/i915/display/intel_display.c intel_crtc_init_scalers(crtc, pipe_config); pipe_config 10419 drivers/gpu/drm/i915/display/intel_display.c pipe_config->shared_dpll = NULL; pipe_config 10421 drivers/gpu/drm/i915/display/intel_display.c active = hsw_get_transcoder_state(crtc, pipe_config, pipe_config 10425 drivers/gpu/drm/i915/display/intel_display.c bxt_get_dsi_transcoder_state(crtc, pipe_config, pipe_config 10434 drivers/gpu/drm/i915/display/intel_display.c if (!transcoder_is_dsi(pipe_config->cpu_transcoder) || pipe_config 10436 drivers/gpu/drm/i915/display/intel_display.c haswell_get_ddi_port_state(crtc, pipe_config); pipe_config 10437 drivers/gpu/drm/i915/display/intel_display.c intel_get_pipe_timings(crtc, pipe_config); pipe_config 10440 drivers/gpu/drm/i915/display/intel_display.c intel_get_pipe_src_size(crtc, pipe_config); pipe_config 10441 drivers/gpu/drm/i915/display/intel_display.c intel_get_crtc_ycbcr_config(crtc, pipe_config); pipe_config 10443 drivers/gpu/drm/i915/display/intel_display.c pipe_config->gamma_mode = I915_READ(GAMMA_MODE(crtc->pipe)); pipe_config 10445 drivers/gpu/drm/i915/display/intel_display.c pipe_config->csc_mode = I915_READ(PIPE_CSC_MODE(crtc->pipe)); pipe_config 10451 drivers/gpu/drm/i915/display/intel_display.c pipe_config->gamma_enable = true; pipe_config 10454 drivers/gpu/drm/i915/display/intel_display.c pipe_config->csc_enable = true; pipe_config 10456 drivers/gpu/drm/i915/display/intel_display.c i9xx_get_pipe_color_config(pipe_config); pipe_config 10459 drivers/gpu/drm/i915/display/intel_display.c intel_color_get_config(pipe_config); pipe_config 10470 drivers/gpu/drm/i915/display/intel_display.c skylake_get_pfit_config(crtc, pipe_config); pipe_config 10472 drivers/gpu/drm/i915/display/intel_display.c ironlake_get_pfit_config(crtc, pipe_config); pipe_config 10477 drivers/gpu/drm/i915/display/intel_display.c pipe_config->ips_enabled = I915_READ(IPS_CTL) & IPS_ENABLE; pipe_config 10484 drivers/gpu/drm/i915/display/intel_display.c pipe_config->ips_enabled = true; pipe_config 10488 drivers/gpu/drm/i915/display/intel_display.c if (pipe_config->cpu_transcoder != TRANSCODER_EDP && pipe_config 10489 drivers/gpu/drm/i915/display/intel_display.c !transcoder_is_dsi(pipe_config->cpu_transcoder)) { pipe_config 10490 drivers/gpu/drm/i915/display/intel_display.c pipe_config->pixel_multiplier = pipe_config 10491 drivers/gpu/drm/i915/display/intel_display.c I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; pipe_config 10493 drivers/gpu/drm/i915/display/intel_display.c pipe_config->pixel_multiplier = 1; pipe_config 11268 drivers/gpu/drm/i915/display/intel_display.c const struct intel_crtc_state *pipe_config) pipe_config 11271 drivers/gpu/drm/i915/display/intel_display.c u32 dpll = pipe_config->dpll_hw_state.dpll; pipe_config 11285 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *pipe_config) pipe_config 11289 drivers/gpu/drm/i915/display/intel_display.c int pipe = pipe_config->cpu_transcoder; pipe_config 11290 drivers/gpu/drm/i915/display/intel_display.c u32 dpll = pipe_config->dpll_hw_state.dpll; pipe_config 11294 drivers/gpu/drm/i915/display/intel_display.c int refclk = i9xx_pll_refclk(dev, pipe_config); pipe_config 11297 drivers/gpu/drm/i915/display/intel_display.c fp = pipe_config->dpll_hw_state.fp0; pipe_config 11299 drivers/gpu/drm/i915/display/intel_display.c fp = pipe_config->dpll_hw_state.fp1; pipe_config 11370 drivers/gpu/drm/i915/display/intel_display.c pipe_config->port_clock = port_clock; pipe_config 11393 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *pipe_config) pipe_config 11398 drivers/gpu/drm/i915/display/intel_display.c i9xx_crtc_clock_get(crtc, pipe_config); pipe_config 11405 drivers/gpu/drm/i915/display/intel_display.c pipe_config->base.adjusted_mode.crtc_clock = pipe_config 11406 drivers/gpu/drm/i915/display/intel_display.c intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), pipe_config 11407 drivers/gpu/drm/i915/display/intel_display.c &pipe_config->fdi_m_n); pipe_config 11772 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *pipe_config = pipe_config 11775 drivers/gpu/drm/i915/display/intel_display.c bool mode_changed = needs_modeset(pipe_config); pipe_config 11779 drivers/gpu/drm/i915/display/intel_display.c pipe_config->update_wm_post = true; pipe_config 11783 drivers/gpu/drm/i915/display/intel_display.c !WARN_ON(pipe_config->shared_dpll)) { pipe_config 11785 drivers/gpu/drm/i915/display/intel_display.c pipe_config); pipe_config 11794 drivers/gpu/drm/i915/display/intel_display.c if (c8_planes_changed(pipe_config)) pipe_config 11797 drivers/gpu/drm/i915/display/intel_display.c if (mode_changed || pipe_config->update_pipe || pipe_config 11799 drivers/gpu/drm/i915/display/intel_display.c ret = intel_color_check(pipe_config); pipe_config 11806 drivers/gpu/drm/i915/display/intel_display.c ret = dev_priv->display.compute_pipe_wm(pipe_config); pipe_config 11822 drivers/gpu/drm/i915/display/intel_display.c ret = dev_priv->display.compute_intermediate_wm(pipe_config); pipe_config 11830 drivers/gpu/drm/i915/display/intel_display.c if (mode_changed || pipe_config->update_pipe) pipe_config 11831 drivers/gpu/drm/i915/display/intel_display.c ret = skl_update_scaler_crtc(pipe_config); pipe_config 11834 drivers/gpu/drm/i915/display/intel_display.c ret = icl_check_nv12_planes(pipe_config); pipe_config 11837 drivers/gpu/drm/i915/display/intel_display.c pipe_config); pipe_config 11840 drivers/gpu/drm/i915/display/intel_display.c pipe_config); pipe_config 11844 drivers/gpu/drm/i915/display/intel_display.c pipe_config->ips_enabled = hsw_compute_ips_config(pipe_config); pipe_config 11880 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *pipe_config) pipe_config 11903 drivers/gpu/drm/i915/display/intel_display.c if (bpp < pipe_config->pipe_bpp) { pipe_config 11908 drivers/gpu/drm/i915/display/intel_display.c pipe_config->pipe_bpp); pipe_config 11910 drivers/gpu/drm/i915/display/intel_display.c pipe_config->pipe_bpp = bpp; pipe_config 11918 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *pipe_config) pipe_config 11921 drivers/gpu/drm/i915/display/intel_display.c struct drm_atomic_state *state = pipe_config->base.state; pipe_config 11934 drivers/gpu/drm/i915/display/intel_display.c pipe_config->pipe_bpp = bpp; pipe_config 11943 drivers/gpu/drm/i915/display/intel_display.c ret = compute_sink_pipe_bpp(connector_state, pipe_config); pipe_config 11964 drivers/gpu/drm/i915/display/intel_display.c intel_dump_m_n_config(const struct intel_crtc_state *pipe_config, pipe_config 12070 drivers/gpu/drm/i915/display/intel_display.c static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config, pipe_config 12074 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); pipe_config 12083 drivers/gpu/drm/i915/display/intel_display.c yesno(pipe_config->base.enable), context); pipe_config 12085 drivers/gpu/drm/i915/display/intel_display.c if (!pipe_config->base.enable) pipe_config 12088 drivers/gpu/drm/i915/display/intel_display.c snprintf_output_types(buf, sizeof(buf), pipe_config->output_types); pipe_config 12090 drivers/gpu/drm/i915/display/intel_display.c yesno(pipe_config->base.active), pipe_config 12091 drivers/gpu/drm/i915/display/intel_display.c buf, pipe_config->output_types, pipe_config 12092 drivers/gpu/drm/i915/display/intel_display.c output_formats(pipe_config->output_format)); pipe_config 12095 drivers/gpu/drm/i915/display/intel_display.c transcoder_name(pipe_config->cpu_transcoder), pipe_config 12096 drivers/gpu/drm/i915/display/intel_display.c pipe_config->pipe_bpp, pipe_config->dither); pipe_config 12098 drivers/gpu/drm/i915/display/intel_display.c if (pipe_config->has_pch_encoder) pipe_config 12099 drivers/gpu/drm/i915/display/intel_display.c intel_dump_m_n_config(pipe_config, "fdi", pipe_config 12100 drivers/gpu/drm/i915/display/intel_display.c pipe_config->fdi_lanes, pipe_config 12101 drivers/gpu/drm/i915/display/intel_display.c &pipe_config->fdi_m_n); pipe_config 12103 drivers/gpu/drm/i915/display/intel_display.c if (intel_crtc_has_dp_encoder(pipe_config)) { pipe_config 12104 drivers/gpu/drm/i915/display/intel_display.c intel_dump_m_n_config(pipe_config, "dp m_n", pipe_config 12105 drivers/gpu/drm/i915/display/intel_display.c pipe_config->lane_count, &pipe_config->dp_m_n); pipe_config 12106 drivers/gpu/drm/i915/display/intel_display.c if (pipe_config->has_drrs) pipe_config 12107 drivers/gpu/drm/i915/display/intel_display.c intel_dump_m_n_config(pipe_config, "dp m2_n2", pipe_config 12108 drivers/gpu/drm/i915/display/intel_display.c pipe_config->lane_count, pipe_config 12109 drivers/gpu/drm/i915/display/intel_display.c &pipe_config->dp_m2_n2); pipe_config 12113 drivers/gpu/drm/i915/display/intel_display.c pipe_config->has_audio, pipe_config->has_infoframe, pipe_config 12114 drivers/gpu/drm/i915/display/intel_display.c pipe_config->infoframes.enable); pipe_config 12116 drivers/gpu/drm/i915/display/intel_display.c if (pipe_config->infoframes.enable & pipe_config 12118 drivers/gpu/drm/i915/display/intel_display.c DRM_DEBUG_KMS("GCP: 0x%x\n", pipe_config->infoframes.gcp); pipe_config 12119 drivers/gpu/drm/i915/display/intel_display.c if (pipe_config->infoframes.enable & pipe_config 12121 drivers/gpu/drm/i915/display/intel_display.c intel_dump_infoframe(dev_priv, &pipe_config->infoframes.avi); pipe_config 12122 drivers/gpu/drm/i915/display/intel_display.c if (pipe_config->infoframes.enable & pipe_config 12124 drivers/gpu/drm/i915/display/intel_display.c intel_dump_infoframe(dev_priv, &pipe_config->infoframes.spd); pipe_config 12125 drivers/gpu/drm/i915/display/intel_display.c if (pipe_config->infoframes.enable & pipe_config 12127 drivers/gpu/drm/i915/display/intel_display.c intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi); pipe_config 12130 drivers/gpu/drm/i915/display/intel_display.c drm_mode_debug_printmodeline(&pipe_config->base.mode); pipe_config 12132 drivers/gpu/drm/i915/display/intel_display.c drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); pipe_config 12133 drivers/gpu/drm/i915/display/intel_display.c intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); pipe_config 12135 drivers/gpu/drm/i915/display/intel_display.c pipe_config->port_clock, pipe_config 12136 drivers/gpu/drm/i915/display/intel_display.c pipe_config->pipe_src_w, pipe_config->pipe_src_h, pipe_config 12137 drivers/gpu/drm/i915/display/intel_display.c pipe_config->pixel_rate); pipe_config 12142 drivers/gpu/drm/i915/display/intel_display.c pipe_config->scaler_state.scaler_users, pipe_config 12143 drivers/gpu/drm/i915/display/intel_display.c pipe_config->scaler_state.scaler_id); pipe_config 12147 drivers/gpu/drm/i915/display/intel_display.c pipe_config->gmch_pfit.control, pipe_config 12148 drivers/gpu/drm/i915/display/intel_display.c pipe_config->gmch_pfit.pgm_ratios, pipe_config 12149 drivers/gpu/drm/i915/display/intel_display.c pipe_config->gmch_pfit.lvds_border_bits); pipe_config 12152 drivers/gpu/drm/i915/display/intel_display.c pipe_config->pch_pfit.pos, pipe_config 12153 drivers/gpu/drm/i915/display/intel_display.c pipe_config->pch_pfit.size, pipe_config 12154 drivers/gpu/drm/i915/display/intel_display.c enableddisabled(pipe_config->pch_pfit.enabled), pipe_config 12155 drivers/gpu/drm/i915/display/intel_display.c yesno(pipe_config->pch_pfit.force_thru)); pipe_config 12158 drivers/gpu/drm/i915/display/intel_display.c pipe_config->ips_enabled, pipe_config->double_wide); pipe_config 12160 drivers/gpu/drm/i915/display/intel_display.c intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state); pipe_config 12274 drivers/gpu/drm/i915/display/intel_display.c intel_modeset_pipe_config(struct intel_crtc_state *pipe_config) pipe_config 12276 drivers/gpu/drm/i915/display/intel_display.c struct drm_crtc *crtc = pipe_config->base.crtc; pipe_config 12277 drivers/gpu/drm/i915/display/intel_display.c struct drm_atomic_state *state = pipe_config->base.state; pipe_config 12285 drivers/gpu/drm/i915/display/intel_display.c ret = clear_intel_crtc_state(pipe_config); pipe_config 12289 drivers/gpu/drm/i915/display/intel_display.c pipe_config->cpu_transcoder = pipe_config 12297 drivers/gpu/drm/i915/display/intel_display.c if (!(pipe_config->base.adjusted_mode.flags & pipe_config 12299 drivers/gpu/drm/i915/display/intel_display.c pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; pipe_config 12301 drivers/gpu/drm/i915/display/intel_display.c if (!(pipe_config->base.adjusted_mode.flags & pipe_config 12303 drivers/gpu/drm/i915/display/intel_display.c pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; pipe_config 12306 drivers/gpu/drm/i915/display/intel_display.c pipe_config); pipe_config 12310 drivers/gpu/drm/i915/display/intel_display.c base_bpp = pipe_config->pipe_bpp; pipe_config 12320 drivers/gpu/drm/i915/display/intel_display.c drm_mode_get_hv_timing(&pipe_config->base.mode, pipe_config 12321 drivers/gpu/drm/i915/display/intel_display.c &pipe_config->pipe_src_w, pipe_config 12322 drivers/gpu/drm/i915/display/intel_display.c &pipe_config->pipe_src_h); pipe_config 12340 drivers/gpu/drm/i915/display/intel_display.c pipe_config->output_types |= pipe_config 12341 drivers/gpu/drm/i915/display/intel_display.c BIT(encoder->compute_output_type(encoder, pipe_config, pipe_config 12344 drivers/gpu/drm/i915/display/intel_display.c pipe_config->output_types |= BIT(encoder->type); pipe_config 12349 drivers/gpu/drm/i915/display/intel_display.c pipe_config->port_clock = 0; pipe_config 12350 drivers/gpu/drm/i915/display/intel_display.c pipe_config->pixel_multiplier = 1; pipe_config 12353 drivers/gpu/drm/i915/display/intel_display.c drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, pipe_config 12365 drivers/gpu/drm/i915/display/intel_display.c ret = encoder->compute_config(encoder, pipe_config, pipe_config 12377 drivers/gpu/drm/i915/display/intel_display.c if (!pipe_config->port_clock) pipe_config 12378 drivers/gpu/drm/i915/display/intel_display.c pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock pipe_config 12379 drivers/gpu/drm/i915/display/intel_display.c * pipe_config->pixel_multiplier; pipe_config 12381 drivers/gpu/drm/i915/display/intel_display.c ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); pipe_config 12402 drivers/gpu/drm/i915/display/intel_display.c pipe_config->dither = (pipe_config->pipe_bpp == 6*3) && pipe_config 12403 drivers/gpu/drm/i915/display/intel_display.c !pipe_config->dither_force_disable; pipe_config 12405 drivers/gpu/drm/i915/display/intel_display.c base_bpp, pipe_config->pipe_bpp, pipe_config->dither); pipe_config 12539 drivers/gpu/drm/i915/display/intel_display.c const struct intel_crtc_state *pipe_config, pipe_config 12546 drivers/gpu/drm/i915/display/intel_display.c !(pipe_config->base.mode.private_flags & I915_MODE_FLAG_INHERITED); pipe_config 12554 drivers/gpu/drm/i915/display/intel_display.c if (current_config->name != pipe_config->name) { \ pipe_config 12558 drivers/gpu/drm/i915/display/intel_display.c pipe_config->name); \ pipe_config 12564 drivers/gpu/drm/i915/display/intel_display.c if (current_config->name != pipe_config->name) { \ pipe_config 12568 drivers/gpu/drm/i915/display/intel_display.c pipe_config->name); \ pipe_config 12574 drivers/gpu/drm/i915/display/intel_display.c if (current_config->name != pipe_config->name) { \ pipe_config 12578 drivers/gpu/drm/i915/display/intel_display.c yesno(pipe_config->name)); \ pipe_config 12589 drivers/gpu/drm/i915/display/intel_display.c if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \ pipe_config 12595 drivers/gpu/drm/i915/display/intel_display.c yesno(pipe_config->name)); \ pipe_config 12601 drivers/gpu/drm/i915/display/intel_display.c if (current_config->name != pipe_config->name) { \ pipe_config 12605 drivers/gpu/drm/i915/display/intel_display.c pipe_config->name); \ pipe_config 12612 drivers/gpu/drm/i915/display/intel_display.c &pipe_config->name,\ pipe_config 12622 drivers/gpu/drm/i915/display/intel_display.c pipe_config->name.tu, \ pipe_config 12623 drivers/gpu/drm/i915/display/intel_display.c pipe_config->name.gmch_m, \ pipe_config 12624 drivers/gpu/drm/i915/display/intel_display.c pipe_config->name.gmch_n, \ pipe_config 12625 drivers/gpu/drm/i915/display/intel_display.c pipe_config->name.link_m, \ pipe_config 12626 drivers/gpu/drm/i915/display/intel_display.c pipe_config->name.link_n); \ pipe_config 12638 drivers/gpu/drm/i915/display/intel_display.c &pipe_config->name, !fastset) && \ pipe_config 12640 drivers/gpu/drm/i915/display/intel_display.c &pipe_config->name, !fastset)) { \ pipe_config 12655 drivers/gpu/drm/i915/display/intel_display.c pipe_config->name.tu, \ pipe_config 12656 drivers/gpu/drm/i915/display/intel_display.c pipe_config->name.gmch_m, \ pipe_config 12657 drivers/gpu/drm/i915/display/intel_display.c pipe_config->name.gmch_n, \ pipe_config 12658 drivers/gpu/drm/i915/display/intel_display.c pipe_config->name.link_m, \ pipe_config 12659 drivers/gpu/drm/i915/display/intel_display.c pipe_config->name.link_n); \ pipe_config 12665 drivers/gpu/drm/i915/display/intel_display.c if ((current_config->name ^ pipe_config->name) & (mask)) { \ pipe_config 12670 drivers/gpu/drm/i915/display/intel_display.c pipe_config->name & (mask)); \ pipe_config 12676 drivers/gpu/drm/i915/display/intel_display.c if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ pipe_config 12680 drivers/gpu/drm/i915/display/intel_display.c pipe_config->name); \ pipe_config 12687 drivers/gpu/drm/i915/display/intel_display.c &pipe_config->infoframes.name)) { \ pipe_config 12690 drivers/gpu/drm/i915/display/intel_display.c &pipe_config->infoframes.name); \ pipe_config 12696 drivers/gpu/drm/i915/display/intel_display.c ((current_config->quirks | pipe_config->quirks) & (quirk)) pipe_config 12858 drivers/gpu/drm/i915/display/intel_display.c const struct intel_crtc_state *pipe_config) pipe_config 12860 drivers/gpu/drm/i915/display/intel_display.c if (pipe_config->has_pch_encoder) { pipe_config 12861 drivers/gpu/drm/i915/display/intel_display.c int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), pipe_config 12862 drivers/gpu/drm/i915/display/intel_display.c &pipe_config->fdi_m_n); pipe_config 12863 drivers/gpu/drm/i915/display/intel_display.c int dotclock = pipe_config->base.adjusted_mode.crtc_clock; pipe_config 13096 drivers/gpu/drm/i915/display/intel_display.c struct intel_crtc_state *pipe_config; pipe_config 13102 drivers/gpu/drm/i915/display/intel_display.c pipe_config = old_crtc_state; pipe_config 13103 drivers/gpu/drm/i915/display/intel_display.c memset(pipe_config, 0, sizeof(*pipe_config)); pipe_config 13104 drivers/gpu/drm/i915/display/intel_display.c pipe_config->base.crtc = &crtc->base; pipe_config 13105 drivers/gpu/drm/i915/display/intel_display.c pipe_config->base.state = state; pipe_config 13109 drivers/gpu/drm/i915/display/intel_display.c active = dev_priv->display.get_pipe_config(crtc, pipe_config); pipe_config 13136 drivers/gpu/drm/i915/display/intel_display.c encoder->get_config(encoder, pipe_config); pipe_config 13139 drivers/gpu/drm/i915/display/intel_display.c intel_crtc_compute_pixel_rate(pipe_config); pipe_config 13144 drivers/gpu/drm/i915/display/intel_display.c intel_pipe_config_sanity_check(dev_priv, pipe_config); pipe_config 13147 drivers/gpu/drm/i915/display/intel_display.c pipe_config, false)) { pipe_config 13149 drivers/gpu/drm/i915/display/intel_display.c intel_dump_pipe_config(pipe_config, NULL, "[hw state]"); pipe_config 499 drivers/gpu/drm/i915/display/intel_display.h struct intel_crtc_state *pipe_config); pipe_config 517 drivers/gpu/drm/i915/display/intel_display.h struct intel_crtc_state *pipe_config); pipe_config 177 drivers/gpu/drm/i915/display/intel_display_types.h struct intel_crtc_state *pipe_config); pipe_config 1287 drivers/gpu/drm/i915/display/intel_display_types.h const struct intel_crtc_state *pipe_config); pipe_config 1728 drivers/gpu/drm/i915/display/intel_dp.c struct intel_crtc_state *pipe_config) pipe_config 1750 drivers/gpu/drm/i915/display/intel_dp.c if (pipe_config->port_clock == divisor[i].clock) { pipe_config 1751 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->dpll = divisor[i].dpll; pipe_config 1752 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->clock_set = true; pipe_config 1833 drivers/gpu/drm/i915/display/intel_dp.c const struct intel_crtc_state *pipe_config) pipe_config 1838 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->cpu_transcoder != TRANSCODER_A; pipe_config 1842 drivers/gpu/drm/i915/display/intel_dp.c const struct intel_crtc_state *pipe_config) pipe_config 1844 drivers/gpu/drm/i915/display/intel_dp.c return intel_dp_source_supports_fec(intel_dp, pipe_config) && pipe_config 1849 drivers/gpu/drm/i915/display/intel_dp.c const struct intel_crtc_state *pipe_config) pipe_config 1854 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->cpu_transcoder != TRANSCODER_A; pipe_config 1858 drivers/gpu/drm/i915/display/intel_dp.c const struct intel_crtc_state *pipe_config) pipe_config 1860 drivers/gpu/drm/i915/display/intel_dp.c if (!intel_dp_is_edp(intel_dp) && !pipe_config->fec_enable) pipe_config 1863 drivers/gpu/drm/i915/display/intel_dp.c return intel_dp_source_supports_dsc(intel_dp, pipe_config) && pipe_config 1868 drivers/gpu/drm/i915/display/intel_dp.c struct intel_crtc_state *pipe_config) pipe_config 1874 drivers/gpu/drm/i915/display/intel_dp.c bpp = pipe_config->pipe_bpp; pipe_config 1896 drivers/gpu/drm/i915/display/intel_dp.c struct intel_crtc_state *pipe_config, pipe_config 1904 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->dither_force_disable = bpp == 6 * 3; pipe_config 1945 drivers/gpu/drm/i915/display/intel_dp.c struct intel_crtc_state *pipe_config, pipe_config 1948 drivers/gpu/drm/i915/display/intel_dp.c struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; pipe_config 1953 drivers/gpu/drm/i915/display/intel_dp.c int output_bpp = intel_dp_output_bpp(pipe_config, bpp); pipe_config 1967 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->lane_count = lane_count; pipe_config 1968 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->pipe_bpp = bpp; pipe_config 1969 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->port_clock = link_clock; pipe_config 1996 drivers/gpu/drm/i915/display/intel_dp.c struct intel_crtc_state *pipe_config, pipe_config 2002 drivers/gpu/drm/i915/display/intel_dp.c struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; pipe_config 2007 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) && pipe_config 2008 drivers/gpu/drm/i915/display/intel_dp.c intel_dp_supports_fec(intel_dp, pipe_config); pipe_config 2010 drivers/gpu/drm/i915/display/intel_dp.c if (!intel_dp_supports_dsc(intel_dp, pipe_config)) pipe_config 2027 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->pipe_bpp = pipe_bpp; pipe_config 2028 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->port_clock = intel_dp->common_rates[limits->max_clock]; pipe_config 2029 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->lane_count = limits->max_lane_count; pipe_config 2032 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->dsc_params.compressed_bpp = pipe_config 2034 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->pipe_bpp); pipe_config 2035 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->dsc_params.slice_count = pipe_config 2043 drivers/gpu/drm/i915/display/intel_dp.c intel_dp_dsc_get_output_bpp(pipe_config->port_clock, pipe_config 2044 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->lane_count, pipe_config 2055 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->dsc_params.compressed_bpp = min_t(u16, pipe_config 2057 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->pipe_bpp); pipe_config 2058 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->dsc_params.slice_count = dsc_dp_slice_count; pipe_config 2066 drivers/gpu/drm/i915/display/intel_dp.c if (pipe_config->dsc_params.slice_count > 1) { pipe_config 2067 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->dsc_params.dsc_split = true; pipe_config 2074 drivers/gpu/drm/i915/display/intel_dp.c ret = intel_dp_compute_dsc_params(intel_dp, pipe_config); pipe_config 2078 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->pipe_bpp, pipe_config 2079 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->dsc_params.compressed_bpp); pipe_config 2083 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->dsc_params.compression_enable = true; pipe_config 2086 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->pipe_bpp, pipe_config 2087 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->dsc_params.compressed_bpp, pipe_config 2088 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->dsc_params.slice_count); pipe_config 2103 drivers/gpu/drm/i915/display/intel_dp.c struct intel_crtc_state *pipe_config, pipe_config 2106 drivers/gpu/drm/i915/display/intel_dp.c struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; pipe_config 2124 drivers/gpu/drm/i915/display/intel_dp.c limits.min_bpp = intel_dp_min_bpp(pipe_config); pipe_config 2125 drivers/gpu/drm/i915/display/intel_dp.c limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config); pipe_config 2139 drivers/gpu/drm/i915/display/intel_dp.c intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits); pipe_config 2151 drivers/gpu/drm/i915/display/intel_dp.c ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits); pipe_config 2156 drivers/gpu/drm/i915/display/intel_dp.c ret = intel_dp_dsc_compute_config(intel_dp, pipe_config, pipe_config 2162 drivers/gpu/drm/i915/display/intel_dp.c if (pipe_config->dsc_params.compression_enable) { pipe_config 2164 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->lane_count, pipe_config->port_clock, pipe_config 2165 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->pipe_bpp, pipe_config 2166 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->dsc_params.compressed_bpp); pipe_config 2170 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->dsc_params.compressed_bpp), pipe_config 2171 drivers/gpu/drm/i915/display/intel_dp.c intel_dp_max_data_rate(pipe_config->port_clock, pipe_config 2172 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->lane_count)); pipe_config 2175 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->lane_count, pipe_config->port_clock, pipe_config 2176 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->pipe_bpp); pipe_config 2180 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->pipe_bpp), pipe_config 2181 drivers/gpu/drm/i915/display/intel_dp.c intel_dp_max_data_rate(pipe_config->port_clock, pipe_config 2182 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->lane_count)); pipe_config 2242 drivers/gpu/drm/i915/display/intel_dp.c struct intel_crtc_state *pipe_config, pipe_config 2246 drivers/gpu/drm/i915/display/intel_dp.c struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; pipe_config 2250 drivers/gpu/drm/i915/display/intel_dp.c struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); pipe_config 2259 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->has_pch_encoder = true; pipe_config 2261 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; pipe_config 2263 drivers/gpu/drm/i915/display/intel_dp.c lspcon_ycbcr420_config(&intel_connector->base, pipe_config); pipe_config 2266 drivers/gpu/drm/i915/display/intel_dp.c pipe_config); pipe_config 2271 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->has_drrs = false; pipe_config 2273 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->has_audio = false; pipe_config 2275 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->has_audio = intel_dp->has_audio; pipe_config 2277 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON; pipe_config 2284 drivers/gpu/drm/i915/display/intel_dp.c ret = skl_update_scaler_crtc(pipe_config); pipe_config 2290 drivers/gpu/drm/i915/display/intel_dp.c intel_gmch_panel_fitting(intel_crtc, pipe_config, pipe_config 2293 drivers/gpu/drm/i915/display/intel_dp.c intel_pch_panel_fitting(intel_crtc, pipe_config, pipe_config 2307 drivers/gpu/drm/i915/display/intel_dp.c ret = intel_dp_compute_link_config(encoder, pipe_config, conn_state); pipe_config 2311 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->limited_color_range = pipe_config 2312 drivers/gpu/drm/i915/display/intel_dp.c intel_dp_limited_color_range(pipe_config, conn_state); pipe_config 2314 drivers/gpu/drm/i915/display/intel_dp.c if (pipe_config->dsc_params.compression_enable) pipe_config 2315 drivers/gpu/drm/i915/display/intel_dp.c output_bpp = pipe_config->dsc_params.compressed_bpp; pipe_config 2317 drivers/gpu/drm/i915/display/intel_dp.c output_bpp = intel_dp_output_bpp(pipe_config, pipe_config->pipe_bpp); pipe_config 2320 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->lane_count, pipe_config 2322 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->port_clock, pipe_config 2323 drivers/gpu/drm/i915/display/intel_dp.c &pipe_config->dp_m_n, pipe_config 2324 drivers/gpu/drm/i915/display/intel_dp.c constant_n, pipe_config->fec_enable); pipe_config 2328 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->has_drrs = true; pipe_config 2330 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->lane_count, pipe_config 2332 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->port_clock, pipe_config 2333 drivers/gpu/drm/i915/display/intel_dp.c &pipe_config->dp_m2_n2, pipe_config 2334 drivers/gpu/drm/i915/display/intel_dp.c constant_n, pipe_config->fec_enable); pipe_config 2338 drivers/gpu/drm/i915/display/intel_dp.c intel_dp_set_clock(encoder, pipe_config); pipe_config 2340 drivers/gpu/drm/i915/display/intel_dp.c intel_psr_compute_config(intel_dp, pipe_config); pipe_config 2356 drivers/gpu/drm/i915/display/intel_dp.c const struct intel_crtc_state *pipe_config) pipe_config 2361 drivers/gpu/drm/i915/display/intel_dp.c struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); pipe_config 2362 drivers/gpu/drm/i915/display/intel_dp.c const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; pipe_config 2364 drivers/gpu/drm/i915/display/intel_dp.c intel_dp_set_link_params(intel_dp, pipe_config->port_clock, pipe_config 2365 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->lane_count, pipe_config 2366 drivers/gpu/drm/i915/display/intel_dp.c intel_crtc_has_type(pipe_config, pipe_config 2393 drivers/gpu/drm/i915/display/intel_dp.c intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count); pipe_config 2420 drivers/gpu/drm/i915/display/intel_dp.c if (IS_G4X(dev_priv) && pipe_config->limited_color_range) pipe_config 2947 drivers/gpu/drm/i915/display/intel_dp.c const struct intel_crtc_state *pipe_config) pipe_config 2949 drivers/gpu/drm/i915/display/intel_dp.c struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); pipe_config 2957 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->port_clock); pipe_config 2961 drivers/gpu/drm/i915/display/intel_dp.c if (pipe_config->port_clock == 162000) pipe_config 3143 drivers/gpu/drm/i915/display/intel_dp.c struct intel_crtc_state *pipe_config) pipe_config 3149 drivers/gpu/drm/i915/display/intel_dp.c struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); pipe_config 3152 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP); pipe_config 3154 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->output_types |= BIT(INTEL_OUTPUT_DP); pipe_config 3158 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A; pipe_config 3184 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->base.adjusted_mode.flags |= flags; pipe_config 3187 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->limited_color_range = true; pipe_config 3189 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->lane_count = pipe_config 3192 drivers/gpu/drm/i915/display/intel_dp.c intel_dp_get_m_n(crtc, pipe_config); pipe_config 3196 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->port_clock = 162000; pipe_config 3198 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->port_clock = 270000; pipe_config 3201 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->base.adjusted_mode.crtc_clock = pipe_config 3202 drivers/gpu/drm/i915/display/intel_dp.c intel_dotclock_calculate(pipe_config->port_clock, pipe_config 3203 drivers/gpu/drm/i915/display/intel_dp.c &pipe_config->dp_m_n); pipe_config 3206 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { pipe_config 3221 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); pipe_config 3222 drivers/gpu/drm/i915/display/intel_dp.c dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp; pipe_config 3411 drivers/gpu/drm/i915/display/intel_dp.c const struct intel_crtc_state *pipe_config, pipe_config 3416 drivers/gpu/drm/i915/display/intel_dp.c struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); pipe_config 3426 drivers/gpu/drm/i915/display/intel_dp.c vlv_init_panel_power_sequencer(encoder, pipe_config); pipe_config 3428 drivers/gpu/drm/i915/display/intel_dp.c intel_dp_enable_port(intel_dp, pipe_config); pipe_config 3439 drivers/gpu/drm/i915/display/intel_dp.c lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count); pipe_config 3449 drivers/gpu/drm/i915/display/intel_dp.c if (pipe_config->has_audio) { pipe_config 3452 drivers/gpu/drm/i915/display/intel_dp.c intel_audio_codec_enable(encoder, pipe_config, conn_state); pipe_config 3457 drivers/gpu/drm/i915/display/intel_dp.c const struct intel_crtc_state *pipe_config, pipe_config 3460 drivers/gpu/drm/i915/display/intel_dp.c intel_enable_dp(encoder, pipe_config, conn_state); pipe_config 3461 drivers/gpu/drm/i915/display/intel_dp.c intel_edp_backlight_on(pipe_config, conn_state); pipe_config 3465 drivers/gpu/drm/i915/display/intel_dp.c const struct intel_crtc_state *pipe_config, pipe_config 3468 drivers/gpu/drm/i915/display/intel_dp.c intel_edp_backlight_on(pipe_config, conn_state); pipe_config 3472 drivers/gpu/drm/i915/display/intel_dp.c const struct intel_crtc_state *pipe_config, pipe_config 3478 drivers/gpu/drm/i915/display/intel_dp.c intel_dp_prepare(encoder, pipe_config); pipe_config 3482 drivers/gpu/drm/i915/display/intel_dp.c ironlake_edp_pll_on(intel_dp, pipe_config); pipe_config 3586 drivers/gpu/drm/i915/display/intel_dp.c const struct intel_crtc_state *pipe_config, pipe_config 3589 drivers/gpu/drm/i915/display/intel_dp.c vlv_phy_pre_encoder_enable(encoder, pipe_config); pipe_config 3591 drivers/gpu/drm/i915/display/intel_dp.c intel_enable_dp(encoder, pipe_config, conn_state); pipe_config 3595 drivers/gpu/drm/i915/display/intel_dp.c const struct intel_crtc_state *pipe_config, pipe_config 3598 drivers/gpu/drm/i915/display/intel_dp.c intel_dp_prepare(encoder, pipe_config); pipe_config 3600 drivers/gpu/drm/i915/display/intel_dp.c vlv_phy_pre_pll_enable(encoder, pipe_config); pipe_config 3604 drivers/gpu/drm/i915/display/intel_dp.c const struct intel_crtc_state *pipe_config, pipe_config 3607 drivers/gpu/drm/i915/display/intel_dp.c chv_phy_pre_encoder_enable(encoder, pipe_config); pipe_config 3609 drivers/gpu/drm/i915/display/intel_dp.c intel_enable_dp(encoder, pipe_config, conn_state); pipe_config 3616 drivers/gpu/drm/i915/display/intel_dp.c const struct intel_crtc_state *pipe_config, pipe_config 3619 drivers/gpu/drm/i915/display/intel_dp.c intel_dp_prepare(encoder, pipe_config); pipe_config 3621 drivers/gpu/drm/i915/display/intel_dp.c chv_phy_pre_pll_enable(encoder, pipe_config); pipe_config 33 drivers/gpu/drm/i915/display/intel_dp.h struct intel_crtc_state *pipe_config, pipe_config 60 drivers/gpu/drm/i915/display/intel_dp.h struct intel_crtc_state *pipe_config, pipe_config 91 drivers/gpu/drm/i915/display/intel_dp_mst.c struct intel_crtc_state *pipe_config, pipe_config 102 drivers/gpu/drm/i915/display/intel_dp_mst.c &pipe_config->base.adjusted_mode; pipe_config 110 drivers/gpu/drm/i915/display/intel_dp_mst.c pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; pipe_config 111 drivers/gpu/drm/i915/display/intel_dp_mst.c pipe_config->has_pch_encoder = false; pipe_config 114 drivers/gpu/drm/i915/display/intel_dp_mst.c pipe_config->has_audio = pipe_config 117 drivers/gpu/drm/i915/display/intel_dp_mst.c pipe_config->has_audio = pipe_config 130 drivers/gpu/drm/i915/display/intel_dp_mst.c limits.min_bpp = intel_dp_min_bpp(pipe_config); pipe_config 139 drivers/gpu/drm/i915/display/intel_dp_mst.c limits.max_bpp = min(pipe_config->pipe_bpp, 24); pipe_config 141 drivers/gpu/drm/i915/display/intel_dp_mst.c intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits); pipe_config 143 drivers/gpu/drm/i915/display/intel_dp_mst.c ret = intel_dp_mst_compute_link_config(encoder, pipe_config, pipe_config 148 drivers/gpu/drm/i915/display/intel_dp_mst.c pipe_config->limited_color_range = pipe_config 149 drivers/gpu/drm/i915/display/intel_dp_mst.c intel_dp_limited_color_range(pipe_config, conn_state); pipe_config 152 drivers/gpu/drm/i915/display/intel_dp_mst.c pipe_config->lane_lat_optim_mask = pipe_config 153 drivers/gpu/drm/i915/display/intel_dp_mst.c bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); pipe_config 155 drivers/gpu/drm/i915/display/intel_dp_mst.c intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); pipe_config 264 drivers/gpu/drm/i915/display/intel_dp_mst.c const struct intel_crtc_state *pipe_config, pipe_config 273 drivers/gpu/drm/i915/display/intel_dp_mst.c pipe_config, NULL); pipe_config 291 drivers/gpu/drm/i915/display/intel_dp_mst.c const struct intel_crtc_state *pipe_config, pipe_config 319 drivers/gpu/drm/i915/display/intel_dp_mst.c pipe_config, NULL); pipe_config 323 drivers/gpu/drm/i915/display/intel_dp_mst.c pipe_config->pbn, pipe_config 324 drivers/gpu/drm/i915/display/intel_dp_mst.c pipe_config->dp_m_n.tu); pipe_config 334 drivers/gpu/drm/i915/display/intel_dp_mst.c intel_ddi_enable_pipe_clock(pipe_config); pipe_config 338 drivers/gpu/drm/i915/display/intel_dp_mst.c const struct intel_crtc_state *pipe_config, pipe_config 356 drivers/gpu/drm/i915/display/intel_dp_mst.c if (pipe_config->has_audio) pipe_config 357 drivers/gpu/drm/i915/display/intel_dp_mst.c intel_audio_codec_enable(encoder, pipe_config, conn_state); pipe_config 371 drivers/gpu/drm/i915/display/intel_dp_mst.c struct intel_crtc_state *pipe_config) pipe_config 376 drivers/gpu/drm/i915/display/intel_dp_mst.c intel_ddi_get_config(&intel_dig_port->base, pipe_config); pipe_config 163 drivers/gpu/drm/i915/display/intel_dvo.c struct intel_crtc_state *pipe_config) pipe_config 169 drivers/gpu/drm/i915/display/intel_dvo.c pipe_config->output_types |= BIT(INTEL_OUTPUT_DVO); pipe_config 181 drivers/gpu/drm/i915/display/intel_dvo.c pipe_config->base.adjusted_mode.flags |= flags; pipe_config 183 drivers/gpu/drm/i915/display/intel_dvo.c pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock; pipe_config 201 drivers/gpu/drm/i915/display/intel_dvo.c const struct intel_crtc_state *pipe_config, pipe_config 210 drivers/gpu/drm/i915/display/intel_dvo.c &pipe_config->base.mode, pipe_config 211 drivers/gpu/drm/i915/display/intel_dvo.c &pipe_config->base.adjusted_mode); pipe_config 250 drivers/gpu/drm/i915/display/intel_dvo.c struct intel_crtc_state *pipe_config, pipe_config 256 drivers/gpu/drm/i915/display/intel_dvo.c struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; pipe_config 270 drivers/gpu/drm/i915/display/intel_dvo.c pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; pipe_config 276 drivers/gpu/drm/i915/display/intel_dvo.c const struct intel_crtc_state *pipe_config, pipe_config 280 drivers/gpu/drm/i915/display/intel_dvo.c struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); pipe_config 281 drivers/gpu/drm/i915/display/intel_dvo.c const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; pipe_config 260 drivers/gpu/drm/i915/display/intel_hdmi.c const struct intel_crtc_state *pipe_config) pipe_config 334 drivers/gpu/drm/i915/display/intel_hdmi.c const struct intel_crtc_state *pipe_config) pipe_config 337 drivers/gpu/drm/i915/display/intel_hdmi.c enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; pipe_config 414 drivers/gpu/drm/i915/display/intel_hdmi.c const struct intel_crtc_state *pipe_config) pipe_config 417 drivers/gpu/drm/i915/display/intel_hdmi.c enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; pipe_config 487 drivers/gpu/drm/i915/display/intel_hdmi.c const struct intel_crtc_state *pipe_config) pipe_config 490 drivers/gpu/drm/i915/display/intel_hdmi.c enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; pipe_config 555 drivers/gpu/drm/i915/display/intel_hdmi.c const struct intel_crtc_state *pipe_config) pipe_config 558 drivers/gpu/drm/i915/display/intel_hdmi.c u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder)); pipe_config 1778 drivers/gpu/drm/i915/display/intel_hdmi.c struct intel_crtc_state *pipe_config) pipe_config 1786 drivers/gpu/drm/i915/display/intel_hdmi.c pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); pipe_config 1801 drivers/gpu/drm/i915/display/intel_hdmi.c pipe_config->has_hdmi_sink = true; pipe_config 1803 drivers/gpu/drm/i915/display/intel_hdmi.c pipe_config->infoframes.enable |= pipe_config 1804 drivers/gpu/drm/i915/display/intel_hdmi.c intel_hdmi_infoframes_enabled(encoder, pipe_config); pipe_config 1806 drivers/gpu/drm/i915/display/intel_hdmi.c if (pipe_config->infoframes.enable) pipe_config 1807 drivers/gpu/drm/i915/display/intel_hdmi.c pipe_config->has_infoframe = true; pipe_config 1810 drivers/gpu/drm/i915/display/intel_hdmi.c pipe_config->has_audio = true; pipe_config 1814 drivers/gpu/drm/i915/display/intel_hdmi.c pipe_config->limited_color_range = true; pipe_config 1816 drivers/gpu/drm/i915/display/intel_hdmi.c pipe_config->base.adjusted_mode.flags |= flags; pipe_config 1819 drivers/gpu/drm/i915/display/intel_hdmi.c dotclock = pipe_config->port_clock * 2 / 3; pipe_config 1821 drivers/gpu/drm/i915/display/intel_hdmi.c dotclock = pipe_config->port_clock; pipe_config 1823 drivers/gpu/drm/i915/display/intel_hdmi.c if (pipe_config->pixel_multiplier) pipe_config 1824 drivers/gpu/drm/i915/display/intel_hdmi.c dotclock /= pipe_config->pixel_multiplier; pipe_config 1826 drivers/gpu/drm/i915/display/intel_hdmi.c pipe_config->base.adjusted_mode.crtc_clock = dotclock; pipe_config 1828 drivers/gpu/drm/i915/display/intel_hdmi.c pipe_config->lane_count = 4; pipe_config 1830 drivers/gpu/drm/i915/display/intel_hdmi.c intel_hdmi_read_gcp_infoframe(encoder, pipe_config); pipe_config 1832 drivers/gpu/drm/i915/display/intel_hdmi.c intel_read_infoframe(encoder, pipe_config, pipe_config 1834 drivers/gpu/drm/i915/display/intel_hdmi.c &pipe_config->infoframes.avi); pipe_config 1835 drivers/gpu/drm/i915/display/intel_hdmi.c intel_read_infoframe(encoder, pipe_config, pipe_config 1837 drivers/gpu/drm/i915/display/intel_hdmi.c &pipe_config->infoframes.spd); pipe_config 1838 drivers/gpu/drm/i915/display/intel_hdmi.c intel_read_infoframe(encoder, pipe_config, pipe_config 1840 drivers/gpu/drm/i915/display/intel_hdmi.c &pipe_config->infoframes.hdmi); pipe_config 1844 drivers/gpu/drm/i915/display/intel_hdmi.c const struct intel_crtc_state *pipe_config, pipe_config 1847 drivers/gpu/drm/i915/display/intel_hdmi.c struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); pipe_config 1849 drivers/gpu/drm/i915/display/intel_hdmi.c WARN_ON(!pipe_config->has_hdmi_sink); pipe_config 1852 drivers/gpu/drm/i915/display/intel_hdmi.c intel_audio_codec_enable(encoder, pipe_config, conn_state); pipe_config 1856 drivers/gpu/drm/i915/display/intel_hdmi.c const struct intel_crtc_state *pipe_config, pipe_config 1867 drivers/gpu/drm/i915/display/intel_hdmi.c if (pipe_config->has_audio) pipe_config 1873 drivers/gpu/drm/i915/display/intel_hdmi.c if (pipe_config->has_audio) pipe_config 1874 drivers/gpu/drm/i915/display/intel_hdmi.c intel_enable_hdmi_audio(encoder, pipe_config, conn_state); pipe_config 1878 drivers/gpu/drm/i915/display/intel_hdmi.c const struct intel_crtc_state *pipe_config, pipe_config 1889 drivers/gpu/drm/i915/display/intel_hdmi.c if (pipe_config->has_audio) pipe_config 1908 drivers/gpu/drm/i915/display/intel_hdmi.c if (pipe_config->pipe_bpp > 24 && pipe_config 1909 drivers/gpu/drm/i915/display/intel_hdmi.c pipe_config->pixel_multiplier > 1) { pipe_config 1923 drivers/gpu/drm/i915/display/intel_hdmi.c if (pipe_config->has_audio) pipe_config 1924 drivers/gpu/drm/i915/display/intel_hdmi.c intel_enable_hdmi_audio(encoder, pipe_config, conn_state); pipe_config 1928 drivers/gpu/drm/i915/display/intel_hdmi.c const struct intel_crtc_state *pipe_config, pipe_config 1933 drivers/gpu/drm/i915/display/intel_hdmi.c struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); pipe_config 1941 drivers/gpu/drm/i915/display/intel_hdmi.c if (pipe_config->has_audio) pipe_config 1954 drivers/gpu/drm/i915/display/intel_hdmi.c if (pipe_config->pipe_bpp > 24) { pipe_config 1966 drivers/gpu/drm/i915/display/intel_hdmi.c if (pipe_config->pipe_bpp > 24) { pipe_config 1978 drivers/gpu/drm/i915/display/intel_hdmi.c if (pipe_config->has_audio) pipe_config 1979 drivers/gpu/drm/i915/display/intel_hdmi.c intel_enable_hdmi_audio(encoder, pipe_config, conn_state); pipe_config 1983 drivers/gpu/drm/i915/display/intel_hdmi.c const struct intel_crtc_state *pipe_config, pipe_config 2295 drivers/gpu/drm/i915/display/intel_hdmi.c struct intel_crtc_state *pipe_config, pipe_config 2300 drivers/gpu/drm/i915/display/intel_hdmi.c struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; pipe_config 2305 drivers/gpu/drm/i915/display/intel_hdmi.c int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock; pipe_config 2314 drivers/gpu/drm/i915/display/intel_hdmi.c pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; pipe_config 2315 drivers/gpu/drm/i915/display/intel_hdmi.c pipe_config->has_hdmi_sink = !force_dvi && intel_hdmi->has_hdmi_sink; pipe_config 2317 drivers/gpu/drm/i915/display/intel_hdmi.c if (pipe_config->has_hdmi_sink) pipe_config 2318 drivers/gpu/drm/i915/display/intel_hdmi.c pipe_config->has_infoframe = true; pipe_config 2322 drivers/gpu/drm/i915/display/intel_hdmi.c pipe_config->limited_color_range = pipe_config 2323 drivers/gpu/drm/i915/display/intel_hdmi.c pipe_config->has_hdmi_sink && pipe_config 2327 drivers/gpu/drm/i915/display/intel_hdmi.c pipe_config->limited_color_range = pipe_config 2332 drivers/gpu/drm/i915/display/intel_hdmi.c pipe_config->pixel_multiplier = 2; pipe_config 2339 drivers/gpu/drm/i915/display/intel_hdmi.c if (!intel_hdmi_ycbcr420_config(connector, pipe_config, pipe_config 2348 drivers/gpu/drm/i915/display/intel_hdmi.c pipe_config->has_pch_encoder = true; pipe_config 2350 drivers/gpu/drm/i915/display/intel_hdmi.c if (pipe_config->has_hdmi_sink) { pipe_config 2352 drivers/gpu/drm/i915/display/intel_hdmi.c pipe_config->has_audio = intel_hdmi->has_audio; pipe_config 2354 drivers/gpu/drm/i915/display/intel_hdmi.c pipe_config->has_audio = pipe_config 2362 drivers/gpu/drm/i915/display/intel_hdmi.c if (hdmi_deep_color_possible(pipe_config, 12) && pipe_config 2369 drivers/gpu/drm/i915/display/intel_hdmi.c pipe_config->port_clock = clock_12bpc; pipe_config 2370 drivers/gpu/drm/i915/display/intel_hdmi.c } else if (hdmi_deep_color_possible(pipe_config, 10) && pipe_config 2377 drivers/gpu/drm/i915/display/intel_hdmi.c pipe_config->port_clock = clock_10bpc; pipe_config 2382 drivers/gpu/drm/i915/display/intel_hdmi.c pipe_config->port_clock = clock_8bpc; pipe_config 2385 drivers/gpu/drm/i915/display/intel_hdmi.c if (!pipe_config->bw_constrained) { pipe_config 2387 drivers/gpu/drm/i915/display/intel_hdmi.c pipe_config->pipe_bpp = desired_bpp; pipe_config 2390 drivers/gpu/drm/i915/display/intel_hdmi.c if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock, pipe_config 2399 drivers/gpu/drm/i915/display/intel_hdmi.c pipe_config->lane_count = 4; pipe_config 2404 drivers/gpu/drm/i915/display/intel_hdmi.c pipe_config->hdmi_scrambling = true; pipe_config 2406 drivers/gpu/drm/i915/display/intel_hdmi.c if (pipe_config->port_clock > 340000) { pipe_config 2407 drivers/gpu/drm/i915/display/intel_hdmi.c pipe_config->hdmi_scrambling = true; pipe_config 2408 drivers/gpu/drm/i915/display/intel_hdmi.c pipe_config->hdmi_high_tmds_clock_ratio = true; pipe_config 2412 drivers/gpu/drm/i915/display/intel_hdmi.c intel_hdmi_compute_gcp_infoframe(encoder, pipe_config, conn_state); pipe_config 2414 drivers/gpu/drm/i915/display/intel_hdmi.c if (!intel_hdmi_compute_avi_infoframe(encoder, pipe_config, conn_state)) { pipe_config 2419 drivers/gpu/drm/i915/display/intel_hdmi.c if (!intel_hdmi_compute_spd_infoframe(encoder, pipe_config, conn_state)) { pipe_config 2424 drivers/gpu/drm/i915/display/intel_hdmi.c if (!intel_hdmi_compute_hdmi_infoframe(encoder, pipe_config, conn_state)) { pipe_config 2429 drivers/gpu/drm/i915/display/intel_hdmi.c if (!intel_hdmi_compute_drm_infoframe(encoder, pipe_config, conn_state)) { pipe_config 2603 drivers/gpu/drm/i915/display/intel_hdmi.c const struct intel_crtc_state *pipe_config, pipe_config 2609 drivers/gpu/drm/i915/display/intel_hdmi.c intel_hdmi_prepare(encoder, pipe_config); pipe_config 2612 drivers/gpu/drm/i915/display/intel_hdmi.c pipe_config->has_infoframe, pipe_config 2613 drivers/gpu/drm/i915/display/intel_hdmi.c pipe_config, conn_state); pipe_config 2617 drivers/gpu/drm/i915/display/intel_hdmi.c const struct intel_crtc_state *pipe_config, pipe_config 2623 drivers/gpu/drm/i915/display/intel_hdmi.c vlv_phy_pre_encoder_enable(encoder, pipe_config); pipe_config 2630 drivers/gpu/drm/i915/display/intel_hdmi.c pipe_config->has_infoframe, pipe_config 2631 drivers/gpu/drm/i915/display/intel_hdmi.c pipe_config, conn_state); pipe_config 2633 drivers/gpu/drm/i915/display/intel_hdmi.c g4x_enable_hdmi(encoder, pipe_config, conn_state); pipe_config 2639 drivers/gpu/drm/i915/display/intel_hdmi.c const struct intel_crtc_state *pipe_config, pipe_config 2642 drivers/gpu/drm/i915/display/intel_hdmi.c intel_hdmi_prepare(encoder, pipe_config); pipe_config 2644 drivers/gpu/drm/i915/display/intel_hdmi.c vlv_phy_pre_pll_enable(encoder, pipe_config); pipe_config 2648 drivers/gpu/drm/i915/display/intel_hdmi.c const struct intel_crtc_state *pipe_config, pipe_config 2651 drivers/gpu/drm/i915/display/intel_hdmi.c intel_hdmi_prepare(encoder, pipe_config); pipe_config 2653 drivers/gpu/drm/i915/display/intel_hdmi.c chv_phy_pre_pll_enable(encoder, pipe_config); pipe_config 2687 drivers/gpu/drm/i915/display/intel_hdmi.c const struct intel_crtc_state *pipe_config, pipe_config 2694 drivers/gpu/drm/i915/display/intel_hdmi.c chv_phy_pre_encoder_enable(encoder, pipe_config); pipe_config 2701 drivers/gpu/drm/i915/display/intel_hdmi.c pipe_config->has_infoframe, pipe_config 2702 drivers/gpu/drm/i915/display/intel_hdmi.c pipe_config, conn_state); pipe_config 2704 drivers/gpu/drm/i915/display/intel_hdmi.c g4x_enable_hdmi(encoder, pipe_config, conn_state); pipe_config 33 drivers/gpu/drm/i915/display/intel_hdmi.h struct intel_crtc_state *pipe_config, pipe_config 522 drivers/gpu/drm/i915/display/intel_lspcon.c const struct intel_crtc_state *pipe_config) pipe_config 34 drivers/gpu/drm/i915/display/intel_lspcon.h const struct intel_crtc_state *pipe_config); pipe_config 120 drivers/gpu/drm/i915/display/intel_lvds.c struct intel_crtc_state *pipe_config) pipe_config 126 drivers/gpu/drm/i915/display/intel_lvds.c pipe_config->output_types |= BIT(INTEL_OUTPUT_LVDS); pipe_config 138 drivers/gpu/drm/i915/display/intel_lvds.c pipe_config->base.adjusted_mode.flags |= flags; pipe_config 141 drivers/gpu/drm/i915/display/intel_lvds.c pipe_config->gmch_pfit.lvds_border_bits = pipe_config 148 drivers/gpu/drm/i915/display/intel_lvds.c pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE; pipe_config 151 drivers/gpu/drm/i915/display/intel_lvds.c pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock; pipe_config 228 drivers/gpu/drm/i915/display/intel_lvds.c const struct intel_crtc_state *pipe_config, pipe_config 233 drivers/gpu/drm/i915/display/intel_lvds.c struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); pipe_config 234 drivers/gpu/drm/i915/display/intel_lvds.c const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; pipe_config 241 drivers/gpu/drm/i915/display/intel_lvds.c pipe_config->shared_dpll); pipe_config 261 drivers/gpu/drm/i915/display/intel_lvds.c temp |= pipe_config->gmch_pfit.lvds_border_bits; pipe_config 291 drivers/gpu/drm/i915/display/intel_lvds.c if (pipe_config->dither && pipe_config->pipe_bpp == 18) pipe_config 309 drivers/gpu/drm/i915/display/intel_lvds.c const struct intel_crtc_state *pipe_config, pipe_config 324 drivers/gpu/drm/i915/display/intel_lvds.c intel_panel_enable_backlight(pipe_config, conn_state); pipe_config 387 drivers/gpu/drm/i915/display/intel_lvds.c struct intel_crtc_state *pipe_config, pipe_config 395 drivers/gpu/drm/i915/display/intel_lvds.c struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; pipe_config 396 drivers/gpu/drm/i915/display/intel_lvds.c struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); pipe_config 410 drivers/gpu/drm/i915/display/intel_lvds.c if (lvds_bpp != pipe_config->pipe_bpp && !pipe_config->bw_constrained) { pipe_config 412 drivers/gpu/drm/i915/display/intel_lvds.c pipe_config->pipe_bpp, lvds_bpp); pipe_config 413 drivers/gpu/drm/i915/display/intel_lvds.c pipe_config->pipe_bpp = lvds_bpp; pipe_config 416 drivers/gpu/drm/i915/display/intel_lvds.c pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; pipe_config 431 drivers/gpu/drm/i915/display/intel_lvds.c pipe_config->has_pch_encoder = true; pipe_config 433 drivers/gpu/drm/i915/display/intel_lvds.c intel_pch_panel_fitting(intel_crtc, pipe_config, pipe_config 436 drivers/gpu/drm/i915/display/intel_lvds.c intel_gmch_panel_fitting(intel_crtc, pipe_config, pipe_config 913 drivers/gpu/drm/i915/display/intel_overlay.c const struct intel_crtc_state *pipe_config = pipe_config 916 drivers/gpu/drm/i915/display/intel_overlay.c if (rec->dst_x < pipe_config->pipe_src_w && pipe_config 917 drivers/gpu/drm/i915/display/intel_overlay.c rec->dst_x + rec->dst_width <= pipe_config->pipe_src_w && pipe_config 918 drivers/gpu/drm/i915/display/intel_overlay.c rec->dst_y < pipe_config->pipe_src_h && pipe_config 919 drivers/gpu/drm/i915/display/intel_overlay.c rec->dst_y + rec->dst_height <= pipe_config->pipe_src_h) pipe_config 178 drivers/gpu/drm/i915/display/intel_panel.c struct intel_crtc_state *pipe_config, pipe_config 181 drivers/gpu/drm/i915/display/intel_panel.c const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; pipe_config 185 drivers/gpu/drm/i915/display/intel_panel.c if (adjusted_mode->crtc_hdisplay == pipe_config->pipe_src_w && pipe_config 186 drivers/gpu/drm/i915/display/intel_panel.c adjusted_mode->crtc_vdisplay == pipe_config->pipe_src_h && pipe_config 187 drivers/gpu/drm/i915/display/intel_panel.c pipe_config->output_format != INTEL_OUTPUT_FORMAT_YCBCR420) pipe_config 192 drivers/gpu/drm/i915/display/intel_panel.c width = pipe_config->pipe_src_w; pipe_config 193 drivers/gpu/drm/i915/display/intel_panel.c height = pipe_config->pipe_src_h; pipe_config 202 drivers/gpu/drm/i915/display/intel_panel.c * pipe_config->pipe_src_h; pipe_config 203 drivers/gpu/drm/i915/display/intel_panel.c u32 scaled_height = pipe_config->pipe_src_w pipe_config 206 drivers/gpu/drm/i915/display/intel_panel.c width = scaled_height / pipe_config->pipe_src_h; pipe_config 213 drivers/gpu/drm/i915/display/intel_panel.c height = scaled_width / pipe_config->pipe_src_w; pipe_config 239 drivers/gpu/drm/i915/display/intel_panel.c pipe_config->pch_pfit.pos = (x << 16) | y; pipe_config 240 drivers/gpu/drm/i915/display/intel_panel.c pipe_config->pch_pfit.size = (width << 16) | height; pipe_config 241 drivers/gpu/drm/i915/display/intel_panel.c pipe_config->pch_pfit.enabled = pipe_config->pch_pfit.size != 0; pipe_config 300 drivers/gpu/drm/i915/display/intel_panel.c static void i965_scale_aspect(struct intel_crtc_state *pipe_config, pipe_config 303 drivers/gpu/drm/i915/display/intel_panel.c const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; pipe_config 305 drivers/gpu/drm/i915/display/intel_panel.c pipe_config->pipe_src_h; pipe_config 306 drivers/gpu/drm/i915/display/intel_panel.c u32 scaled_height = pipe_config->pipe_src_w * pipe_config 316 drivers/gpu/drm/i915/display/intel_panel.c else if (adjusted_mode->crtc_hdisplay != pipe_config->pipe_src_w) pipe_config 320 drivers/gpu/drm/i915/display/intel_panel.c static void i9xx_scale_aspect(struct intel_crtc_state *pipe_config, pipe_config 324 drivers/gpu/drm/i915/display/intel_panel.c struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; pipe_config 326 drivers/gpu/drm/i915/display/intel_panel.c pipe_config->pipe_src_h; pipe_config 327 drivers/gpu/drm/i915/display/intel_panel.c u32 scaled_height = pipe_config->pipe_src_w * pipe_config 339 drivers/gpu/drm/i915/display/intel_panel.c pipe_config->pipe_src_h); pipe_config 342 drivers/gpu/drm/i915/display/intel_panel.c if (pipe_config->pipe_src_h != adjusted_mode->crtc_vdisplay) { pipe_config 343 drivers/gpu/drm/i915/display/intel_panel.c bits = panel_fitter_scaling(pipe_config->pipe_src_h, pipe_config 355 drivers/gpu/drm/i915/display/intel_panel.c pipe_config->pipe_src_w); pipe_config 358 drivers/gpu/drm/i915/display/intel_panel.c if (pipe_config->pipe_src_w != adjusted_mode->crtc_hdisplay) { pipe_config 359 drivers/gpu/drm/i915/display/intel_panel.c bits = panel_fitter_scaling(pipe_config->pipe_src_w, pipe_config 378 drivers/gpu/drm/i915/display/intel_panel.c struct intel_crtc_state *pipe_config, pipe_config 383 drivers/gpu/drm/i915/display/intel_panel.c struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; pipe_config 386 drivers/gpu/drm/i915/display/intel_panel.c if (adjusted_mode->crtc_hdisplay == pipe_config->pipe_src_w && pipe_config 387 drivers/gpu/drm/i915/display/intel_panel.c adjusted_mode->crtc_vdisplay == pipe_config->pipe_src_h) pipe_config 396 drivers/gpu/drm/i915/display/intel_panel.c centre_horizontally(adjusted_mode, pipe_config->pipe_src_w); pipe_config 397 drivers/gpu/drm/i915/display/intel_panel.c centre_vertically(adjusted_mode, pipe_config->pipe_src_h); pipe_config 403 drivers/gpu/drm/i915/display/intel_panel.c i965_scale_aspect(pipe_config, &pfit_control); pipe_config 405 drivers/gpu/drm/i915/display/intel_panel.c i9xx_scale_aspect(pipe_config, &pfit_control, pipe_config 413 drivers/gpu/drm/i915/display/intel_panel.c if (pipe_config->pipe_src_h != adjusted_mode->crtc_vdisplay || pipe_config 414 drivers/gpu/drm/i915/display/intel_panel.c pipe_config->pipe_src_w != adjusted_mode->crtc_hdisplay) { pipe_config 443 drivers/gpu/drm/i915/display/intel_panel.c if (INTEL_GEN(dev_priv) < 4 && pipe_config->pipe_bpp == 18) pipe_config 446 drivers/gpu/drm/i915/display/intel_panel.c pipe_config->gmch_pfit.control = pfit_control; pipe_config 447 drivers/gpu/drm/i915/display/intel_panel.c pipe_config->gmch_pfit.pgm_ratios = pfit_pgm_ratios; pipe_config 448 drivers/gpu/drm/i915/display/intel_panel.c pipe_config->gmch_pfit.lvds_border_bits = border; pipe_config 29 drivers/gpu/drm/i915/display/intel_panel.h struct intel_crtc_state *pipe_config, pipe_config 32 drivers/gpu/drm/i915/display/intel_panel.h struct intel_crtc_state *pipe_config, pipe_config 290 drivers/gpu/drm/i915/display/intel_pipe_crc.c struct intel_crtc_state *pipe_config; pipe_config 306 drivers/gpu/drm/i915/display/intel_pipe_crc.c pipe_config = intel_atomic_get_crtc_state(state, crtc); pipe_config 307 drivers/gpu/drm/i915/display/intel_pipe_crc.c if (IS_ERR(pipe_config)) { pipe_config 308 drivers/gpu/drm/i915/display/intel_pipe_crc.c ret = PTR_ERR(pipe_config); pipe_config 312 drivers/gpu/drm/i915/display/intel_pipe_crc.c pipe_config->base.mode_changed = pipe_config->has_psr; pipe_config 313 drivers/gpu/drm/i915/display/intel_pipe_crc.c pipe_config->crc_enabled = enable; pipe_config 316 drivers/gpu/drm/i915/display/intel_pipe_crc.c pipe_config->base.active && crtc->pipe == PIPE_A && pipe_config 317 drivers/gpu/drm/i915/display/intel_pipe_crc.c pipe_config->cpu_transcoder == TRANSCODER_EDP) pipe_config 318 drivers/gpu/drm/i915/display/intel_pipe_crc.c pipe_config->base.mode_changed = true; pipe_config 1242 drivers/gpu/drm/i915/display/intel_sdvo.c static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_state *pipe_config) pipe_config 1244 drivers/gpu/drm/i915/display/intel_sdvo.c unsigned dotclock = pipe_config->port_clock; pipe_config 1245 drivers/gpu/drm/i915/display/intel_sdvo.c struct dpll *clock = &pipe_config->dpll; pipe_config 1267 drivers/gpu/drm/i915/display/intel_sdvo.c pipe_config->clock_set = true; pipe_config 1271 drivers/gpu/drm/i915/display/intel_sdvo.c struct intel_crtc_state *pipe_config, pipe_config 1279 drivers/gpu/drm/i915/display/intel_sdvo.c struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; pipe_config 1280 drivers/gpu/drm/i915/display/intel_sdvo.c struct drm_display_mode *mode = &pipe_config->base.mode; pipe_config 1283 drivers/gpu/drm/i915/display/intel_sdvo.c pipe_config->pipe_bpp = 8*3; pipe_config 1284 drivers/gpu/drm/i915/display/intel_sdvo.c pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; pipe_config 1287 drivers/gpu/drm/i915/display/intel_sdvo.c pipe_config->has_pch_encoder = true; pipe_config 1303 drivers/gpu/drm/i915/display/intel_sdvo.c pipe_config->sdvo_tv_clock = true; pipe_config 1322 drivers/gpu/drm/i915/display/intel_sdvo.c pipe_config->pixel_multiplier = pipe_config 1326 drivers/gpu/drm/i915/display/intel_sdvo.c pipe_config->has_hdmi_sink = intel_sdvo->has_hdmi_monitor; pipe_config 1330 drivers/gpu/drm/i915/display/intel_sdvo.c pipe_config->has_audio = true; pipe_config 1339 drivers/gpu/drm/i915/display/intel_sdvo.c if (pipe_config->has_hdmi_sink && pipe_config 1341 drivers/gpu/drm/i915/display/intel_sdvo.c pipe_config->limited_color_range = true; pipe_config 1343 drivers/gpu/drm/i915/display/intel_sdvo.c if (pipe_config->has_hdmi_sink && pipe_config 1345 drivers/gpu/drm/i915/display/intel_sdvo.c pipe_config->limited_color_range = true; pipe_config 1350 drivers/gpu/drm/i915/display/intel_sdvo.c i9xx_adjust_sdvo_tv_clock(pipe_config); pipe_config 1357 drivers/gpu/drm/i915/display/intel_sdvo.c pipe_config, conn_state)) { pipe_config 1596 drivers/gpu/drm/i915/display/intel_sdvo.c struct intel_crtc_state *pipe_config) pipe_config 1608 drivers/gpu/drm/i915/display/intel_sdvo.c pipe_config->output_types |= BIT(INTEL_OUTPUT_SDVO); pipe_config 1619 drivers/gpu/drm/i915/display/intel_sdvo.c pipe_config->quirks |= PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS; pipe_config 1632 drivers/gpu/drm/i915/display/intel_sdvo.c pipe_config->base.adjusted_mode.flags |= flags; pipe_config 1642 drivers/gpu/drm/i915/display/intel_sdvo.c pipe_config->pixel_multiplier = pipe_config 1647 drivers/gpu/drm/i915/display/intel_sdvo.c dotclock = pipe_config->port_clock; pipe_config 1649 drivers/gpu/drm/i915/display/intel_sdvo.c if (pipe_config->pixel_multiplier) pipe_config 1650 drivers/gpu/drm/i915/display/intel_sdvo.c dotclock /= pipe_config->pixel_multiplier; pipe_config 1652 drivers/gpu/drm/i915/display/intel_sdvo.c pipe_config->base.adjusted_mode.crtc_clock = dotclock; pipe_config 1670 drivers/gpu/drm/i915/display/intel_sdvo.c WARN(encoder_pixel_multiplier != pipe_config->pixel_multiplier, pipe_config 1672 drivers/gpu/drm/i915/display/intel_sdvo.c pipe_config->pixel_multiplier, encoder_pixel_multiplier); pipe_config 1675 drivers/gpu/drm/i915/display/intel_sdvo.c pipe_config->limited_color_range = true; pipe_config 1682 drivers/gpu/drm/i915/display/intel_sdvo.c pipe_config->has_audio = true; pipe_config 1688 drivers/gpu/drm/i915/display/intel_sdvo.c pipe_config->has_hdmi_sink = true; pipe_config 1691 drivers/gpu/drm/i915/display/intel_sdvo.c intel_sdvo_get_avi_infoframe(intel_sdvo, pipe_config); pipe_config 1782 drivers/gpu/drm/i915/display/intel_sdvo.c const struct intel_crtc_state *pipe_config, pipe_config 1788 drivers/gpu/drm/i915/display/intel_sdvo.c struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); pipe_config 1818 drivers/gpu/drm/i915/display/intel_sdvo.c if (pipe_config->has_audio) pipe_config 1819 drivers/gpu/drm/i915/display/intel_sdvo.c intel_sdvo_enable_audio(intel_sdvo, pipe_config, conn_state); pipe_config 919 drivers/gpu/drm/i915/display/intel_tv.c const struct intel_crtc_state *pipe_config, pipe_config 927 drivers/gpu/drm/i915/display/intel_tv.c to_intel_crtc(pipe_config->base.crtc)->pipe); pipe_config 1085 drivers/gpu/drm/i915/display/intel_tv.c struct intel_crtc_state *pipe_config) pipe_config 1089 drivers/gpu/drm/i915/display/intel_tv.c &pipe_config->base.adjusted_mode; pipe_config 1097 drivers/gpu/drm/i915/display/intel_tv.c pipe_config->output_types |= BIT(INTEL_OUTPUT_TVOUT); pipe_config 1119 drivers/gpu/drm/i915/display/intel_tv.c tv_mode.clock = pipe_config->port_clock; pipe_config 1184 drivers/gpu/drm/i915/display/intel_tv.c struct intel_crtc_state *pipe_config, pipe_config 1192 drivers/gpu/drm/i915/display/intel_tv.c &pipe_config->base.adjusted_mode; pipe_config 1202 drivers/gpu/drm/i915/display/intel_tv.c pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; pipe_config 1205 drivers/gpu/drm/i915/display/intel_tv.c pipe_config->pipe_bpp = 8*3; pipe_config 1207 drivers/gpu/drm/i915/display/intel_tv.c pipe_config->port_clock = tv_mode->clock; pipe_config 1417 drivers/gpu/drm/i915/display/intel_tv.c const struct intel_crtc_state *pipe_config, pipe_config 1421 drivers/gpu/drm/i915/display/intel_tv.c struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); pipe_config 323 drivers/gpu/drm/i915/display/intel_vdsc.c struct intel_crtc_state *pipe_config) pipe_config 325 drivers/gpu/drm/i915/display/intel_vdsc.c struct drm_dsc_config *vdsc_cfg = &pipe_config->dp_dsc_cfg; pipe_config 326 drivers/gpu/drm/i915/display/intel_vdsc.c u16 compressed_bpp = pipe_config->dsc_params.compressed_bpp; pipe_config 332 drivers/gpu/drm/i915/display/intel_vdsc.c vdsc_cfg->pic_width = pipe_config->base.adjusted_mode.crtc_hdisplay; pipe_config 333 drivers/gpu/drm/i915/display/intel_vdsc.c vdsc_cfg->pic_height = pipe_config->base.adjusted_mode.crtc_vdisplay; pipe_config 335 drivers/gpu/drm/i915/display/intel_vdsc.c pipe_config->dsc_params.slice_count); pipe_config 382 drivers/gpu/drm/i915/display/intel_vdsc.c vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3; pipe_config 17 drivers/gpu/drm/i915/display/intel_vdsc.h struct intel_crtc_state *pipe_config); pipe_config 257 drivers/gpu/drm/i915/display/vlv_dsi.c struct intel_crtc_state *pipe_config, pipe_config 264 drivers/gpu/drm/i915/display/vlv_dsi.c struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); pipe_config 266 drivers/gpu/drm/i915/display/vlv_dsi.c struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; pipe_config 270 drivers/gpu/drm/i915/display/vlv_dsi.c pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; pipe_config 276 drivers/gpu/drm/i915/display/vlv_dsi.c intel_gmch_panel_fitting(crtc, pipe_config, pipe_config 279 drivers/gpu/drm/i915/display/vlv_dsi.c intel_pch_panel_fitting(crtc, pipe_config, pipe_config 290 drivers/gpu/drm/i915/display/vlv_dsi.c pipe_config->pipe_bpp = 24; pipe_config 292 drivers/gpu/drm/i915/display/vlv_dsi.c pipe_config->pipe_bpp = 18; pipe_config 301 drivers/gpu/drm/i915/display/vlv_dsi.c pipe_config->cpu_transcoder = TRANSCODER_DSI_C; pipe_config 303 drivers/gpu/drm/i915/display/vlv_dsi.c pipe_config->cpu_transcoder = TRANSCODER_DSI_A; pipe_config 305 drivers/gpu/drm/i915/display/vlv_dsi.c ret = bxt_dsi_pll_compute(encoder, pipe_config); pipe_config 309 drivers/gpu/drm/i915/display/vlv_dsi.c ret = vlv_dsi_pll_compute(encoder, pipe_config); pipe_config 314 drivers/gpu/drm/i915/display/vlv_dsi.c pipe_config->clock_set = true; pipe_config 700 drivers/gpu/drm/i915/display/vlv_dsi.c const struct intel_crtc_state *pipe_config); pipe_config 745 drivers/gpu/drm/i915/display/vlv_dsi.c const struct intel_crtc_state *pipe_config, pipe_config 749 drivers/gpu/drm/i915/display/vlv_dsi.c struct drm_crtc *crtc = pipe_config->base.crtc; pipe_config 767 drivers/gpu/drm/i915/display/vlv_dsi.c bxt_dsi_pll_enable(encoder, pipe_config); pipe_config 770 drivers/gpu/drm/i915/display/vlv_dsi.c vlv_dsi_pll_enable(encoder, pipe_config); pipe_config 794 drivers/gpu/drm/i915/display/vlv_dsi.c intel_dsi_prepare(encoder, pipe_config); pipe_config 810 drivers/gpu/drm/i915/display/vlv_dsi.c intel_dsi_prepare(encoder, pipe_config); pipe_config 818 drivers/gpu/drm/i915/display/vlv_dsi.c intel_dsi_prepare(encoder, pipe_config); pipe_config 838 drivers/gpu/drm/i915/display/vlv_dsi.c intel_dsi_port_enable(encoder, pipe_config); pipe_config 841 drivers/gpu/drm/i915/display/vlv_dsi.c intel_panel_enable_backlight(pipe_config, conn_state); pipe_config 885 drivers/gpu/drm/i915/display/vlv_dsi.c const struct intel_crtc_state *pipe_config, pipe_config 1030 drivers/gpu/drm/i915/display/vlv_dsi.c struct intel_crtc_state *pipe_config) pipe_config 1035 drivers/gpu/drm/i915/display/vlv_dsi.c &pipe_config->base.adjusted_mode; pipe_config 1037 drivers/gpu/drm/i915/display/vlv_dsi.c struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); pipe_config 1063 drivers/gpu/drm/i915/display/vlv_dsi.c pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc); pipe_config 1191 drivers/gpu/drm/i915/display/vlv_dsi.c struct intel_crtc_state *pipe_config) pipe_config 1197 drivers/gpu/drm/i915/display/vlv_dsi.c pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI); pipe_config 1200 drivers/gpu/drm/i915/display/vlv_dsi.c bxt_dsi_get_pipe_config(encoder, pipe_config); pipe_config 1201 drivers/gpu/drm/i915/display/vlv_dsi.c pclk = bxt_dsi_get_pclk(encoder, pipe_config); pipe_config 1203 drivers/gpu/drm/i915/display/vlv_dsi.c pclk = vlv_dsi_get_pclk(encoder, pipe_config); pipe_config 1207 drivers/gpu/drm/i915/display/vlv_dsi.c pipe_config->base.adjusted_mode.crtc_clock = pclk; pipe_config 1208 drivers/gpu/drm/i915/display/vlv_dsi.c pipe_config->port_clock = pclk; pipe_config 1313 drivers/gpu/drm/i915/display/vlv_dsi.c const struct intel_crtc_state *pipe_config) pipe_config 1318 drivers/gpu/drm/i915/display/vlv_dsi.c struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); pipe_config 1320 drivers/gpu/drm/i915/display/vlv_dsi.c const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; pipe_config 2691 drivers/gpu/drm/i915/i915_debugfs.c struct intel_crtc_state *pipe_config; pipe_config 2695 drivers/gpu/drm/i915/i915_debugfs.c pipe_config = to_intel_crtc_state(intel_crtc->base.state); pipe_config 2701 drivers/gpu/drm/i915/i915_debugfs.c pipe_config->scaler_state.scaler_users, pipe_config 2702 drivers/gpu/drm/i915/i915_debugfs.c pipe_config->scaler_state.scaler_id); pipe_config 2706 drivers/gpu/drm/i915/i915_debugfs.c &pipe_config->scaler_state.scalers[i]; pipe_config 2731 drivers/gpu/drm/i915/i915_debugfs.c struct intel_crtc_state *pipe_config; pipe_config 2734 drivers/gpu/drm/i915/i915_debugfs.c pipe_config = to_intel_crtc_state(crtc->base.state); pipe_config 2738 drivers/gpu/drm/i915/i915_debugfs.c yesno(pipe_config->base.active), pipe_config 2739 drivers/gpu/drm/i915/i915_debugfs.c pipe_config->pipe_src_w, pipe_config->pipe_src_h, pipe_config 2740 drivers/gpu/drm/i915/i915_debugfs.c yesno(pipe_config->dither), pipe_config->pipe_bpp); pipe_config 2742 drivers/gpu/drm/i915/i915_debugfs.c if (pipe_config->base.active) { pipe_config 283 drivers/gpu/drm/i915/i915_drv.h void (*crtc_enable)(struct intel_crtc_state *pipe_config, pipe_config 1357 drivers/gpu/drm/radeon/atombios_crtc.c u32 pipe_config = (rdev->config.cik.tile_mode_array[10] >> 6) & 0x1f; pipe_config 1359 drivers/gpu/drm/radeon/atombios_crtc.c fb_format |= CIK_GRPH_PIPE_CONFIG(pipe_config); pipe_config 1781 drivers/staging/media/ipu3/ipu3-abi.h u32 pipe_config; /* the pipe config */ pipe_config 1065 drivers/staging/media/ipu3/ipu3-css.c sp_group->pipe[pipe].pipe_config = pipe_config 1067 drivers/staging/media/ipu3/ipu3-css.c sp_group->pipe[pipe].pipe_config |= IMGU_ABI_PIPE_CONFIG_ACQUIRE_ISP; pipe_config 477 drivers/usb/renesas_usbhs/pipe.c struct renesas_usbhs_driver_pipe_config *pipe_config = pipe_config 489 drivers/usb/renesas_usbhs/pipe.c buff_size = pipe_config->bufsize; pipe_config 490 drivers/usb/renesas_usbhs/pipe.c bufnmb = pipe_config->bufnum; pipe_config 507 drivers/usb/renesas_usbhs/pipe.c struct renesas_usbhs_driver_pipe_config *pipe_config = pipe_config 509 drivers/usb/renesas_usbhs/pipe.c u16 dblb = pipe_config->double_buf ? DBLB : 0;