pior 25 drivers/gpu/drm/nouveau/dispnv50/core.h } *dac, *pior, *sor; pior 84 drivers/gpu/drm/nouveau/dispnv50/core507d.c .pior = &pior507d, pior 34 drivers/gpu/drm/nouveau/dispnv50/core827d.c .pior = &pior507d, pior 1666 drivers/gpu/drm/nouveau/dispnv50/disp.c core->func->pior->ctrl(core, nv_encoder->or, 0x00000000, NULL); pior 1702 drivers/gpu/drm/nouveau/dispnv50/disp.c core->func->pior->ctrl(core, nv_encoder->or, (proto << 8) | owner, asyh); pior 40 drivers/gpu/drm/nouveau/nvkm/engine/disp/g84.c .pior = { .cnt = nv50_pior_cnt, .new = nv50_pior_new }, pior 40 drivers/gpu/drm/nouveau/nvkm/engine/disp/g94.c .pior = { .cnt = nv50_pior_cnt, .new = nv50_pior_new }, pior 40 drivers/gpu/drm/nouveau/nvkm/engine/disp/gt200.c .pior = { .cnt = nv50_pior_cnt, .new = nv50_pior_new }, pior 40 drivers/gpu/drm/nouveau/nvkm/engine/disp/gt215.c .pior = { .cnt = nv50_pior_cnt, .new = nv50_pior_new }, pior 45 drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.c nvkm_ior_del(struct nvkm_ior **pior) pior 47 drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.c struct nvkm_ior *ior = *pior; pior 51 drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.c kfree(*pior); pior 52 drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.c *pior = NULL; pior 38 drivers/gpu/drm/nouveau/nvkm/engine/disp/mcp77.c .pior = { .cnt = nv50_pior_cnt, .new = nv50_pior_new }, pior 38 drivers/gpu/drm/nouveau/nvkm/engine/disp/mcp89.c .pior = { .cnt = nv50_pior_cnt, .new = nv50_pior_new }, pior 116 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c if (func->pior.cnt) { pior 117 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c disp->pior.nr = func->pior.cnt(&disp->base, &disp->pior.mask); pior 119 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c disp->pior.nr, disp->pior.mask); pior 120 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c for_each_set_bit(i, &disp->pior.mask, disp->pior.nr) { pior 121 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c ret = func->pior.new(&disp->base, i); pior 732 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c for (i = 0; i < disp->pior.nr; i++) { pior 768 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c .pior = { .cnt = nv50_pior_cnt, .new = nv50_pior_new }, pior 35 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.h } pior; pior 67 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.h } wndw, head, dac, sor, pior; pior 31 drivers/gpu/drm/nouveau/nvkm/engine/disp/piornv50.c nv50_pior_clock(struct nvkm_ior *pior) pior 33 drivers/gpu/drm/nouveau/nvkm/engine/disp/piornv50.c struct nvkm_device *device = pior->disp->engine.subdev.device; pior 34 drivers/gpu/drm/nouveau/nvkm/engine/disp/piornv50.c const u32 poff = nv50_ior_base(pior); pior 39 drivers/gpu/drm/nouveau/nvkm/engine/disp/piornv50.c nv50_pior_dp_links(struct nvkm_ior *pior, struct nvkm_i2c_aux *aux) pior 41 drivers/gpu/drm/nouveau/nvkm/engine/disp/piornv50.c int ret = nvkm_i2c_aux_lnk_ctl(aux, pior->dp.nr, pior->dp.bw, pior 42 drivers/gpu/drm/nouveau/nvkm/engine/disp/piornv50.c pior->dp.ef); pior 58 drivers/gpu/drm/nouveau/nvkm/engine/disp/piornv50.c nv50_pior_power(struct nvkm_ior *pior, bool normal, bool pu, pior 61 drivers/gpu/drm/nouveau/nvkm/engine/disp/piornv50.c struct nvkm_device *device = pior->disp->engine.subdev.device; pior 62 drivers/gpu/drm/nouveau/nvkm/engine/disp/piornv50.c const u32 poff = nv50_ior_base(pior); pior 98 drivers/gpu/drm/nouveau/nvkm/engine/disp/piornv50.c nv50_pior_state(struct nvkm_ior *pior, struct nvkm_ior_state *state) pior 100 drivers/gpu/drm/nouveau/nvkm/engine/disp/piornv50.c struct nvkm_device *device = pior->disp->engine.subdev.device; pior 101 drivers/gpu/drm/nouveau/nvkm/engine/disp/piornv50.c const u32 coff = pior->id * 8 + (state == &pior->arm) * 4; pior 114 drivers/gpu/drm/nouveau/nvkm/engine/disp/piornv50.c nv50_pior_depth(pior, state, ctrl);