piommu            156 arch/x86/events/amd/iommu.c 	struct perf_amd_iommu *piommu = container_of(event->pmu, struct perf_amd_iommu, pmu);
piommu            157 arch/x86/events/amd/iommu.c 	int max_cntrs = piommu->max_counters;
piommu            158 arch/x86/events/amd/iommu.c 	int max_banks = piommu->max_banks;
piommu            163 arch/x86/events/amd/iommu.c 	raw_spin_lock_irqsave(&piommu->lock, flags);
piommu            168 arch/x86/events/amd/iommu.c 			if (piommu->cntr_assign_mask & BIT_ULL(shift)) {
piommu            171 arch/x86/events/amd/iommu.c 				piommu->cntr_assign_mask |= BIT_ULL(shift);
piommu            181 arch/x86/events/amd/iommu.c 	raw_spin_unlock_irqrestore(&piommu->lock, flags);