pin_reg           167 drivers/pinctrl/freescale/pinctrl-imx.c 	const struct imx_pin_reg *pin_reg;
pin_reg           171 drivers/pinctrl/freescale/pinctrl-imx.c 	pin_reg = &ipctl->pin_regs[pin_id];
pin_reg           173 drivers/pinctrl/freescale/pinctrl-imx.c 	if (pin_reg->mux_reg == -1) {
pin_reg           182 drivers/pinctrl/freescale/pinctrl-imx.c 		reg = readl(ipctl->base + pin_reg->mux_reg);
pin_reg           185 drivers/pinctrl/freescale/pinctrl-imx.c 		writel(reg, ipctl->base + pin_reg->mux_reg);
pin_reg           187 drivers/pinctrl/freescale/pinctrl-imx.c 			pin_reg->mux_reg, reg);
pin_reg           189 drivers/pinctrl/freescale/pinctrl-imx.c 		writel(pin_mmio->mux_mode, ipctl->base + pin_reg->mux_reg);
pin_reg           191 drivers/pinctrl/freescale/pinctrl-imx.c 			pin_reg->mux_reg, pin_mmio->mux_mode);
pin_reg           353 drivers/pinctrl/freescale/pinctrl-imx.c 	const struct imx_pin_reg *pin_reg = &ipctl->pin_regs[pin_id];
pin_reg           355 drivers/pinctrl/freescale/pinctrl-imx.c 	if (pin_reg->conf_reg == -1) {
pin_reg           361 drivers/pinctrl/freescale/pinctrl-imx.c 	*config = readl(ipctl->base + pin_reg->conf_reg);
pin_reg           387 drivers/pinctrl/freescale/pinctrl-imx.c 	const struct imx_pin_reg *pin_reg = &ipctl->pin_regs[pin_id];
pin_reg           390 drivers/pinctrl/freescale/pinctrl-imx.c 	if (pin_reg->conf_reg == -1) {
pin_reg           402 drivers/pinctrl/freescale/pinctrl-imx.c 			reg = readl(ipctl->base + pin_reg->conf_reg);
pin_reg           405 drivers/pinctrl/freescale/pinctrl-imx.c 			writel(reg, ipctl->base + pin_reg->conf_reg);
pin_reg           407 drivers/pinctrl/freescale/pinctrl-imx.c 				pin_reg->conf_reg, reg);
pin_reg           409 drivers/pinctrl/freescale/pinctrl-imx.c 			writel(configs[i], ipctl->base + pin_reg->conf_reg);
pin_reg           411 drivers/pinctrl/freescale/pinctrl-imx.c 				pin_reg->conf_reg, configs[i]);
pin_reg           438 drivers/pinctrl/freescale/pinctrl-imx.c 	const struct imx_pin_reg *pin_reg;
pin_reg           451 drivers/pinctrl/freescale/pinctrl-imx.c 		pin_reg = &ipctl->pin_regs[pin_id];
pin_reg           452 drivers/pinctrl/freescale/pinctrl-imx.c 		if (pin_reg->conf_reg == -1) {
pin_reg           457 drivers/pinctrl/freescale/pinctrl-imx.c 		config = readl(ipctl->base + pin_reg->conf_reg);
pin_reg           521 drivers/pinctrl/freescale/pinctrl-imx.c 	struct imx_pin_reg *pin_reg;
pin_reg           540 drivers/pinctrl/freescale/pinctrl-imx.c 	pin_reg = &ipctl->pin_regs[*pin_id];
pin_reg           542 drivers/pinctrl/freescale/pinctrl-imx.c 	pin_reg->mux_reg = mux_reg;
pin_reg           543 drivers/pinctrl/freescale/pinctrl-imx.c 	pin_reg->conf_reg = conf_reg;
pin_reg           267 drivers/pinctrl/freescale/pinctrl-imx7ulp.c 	const struct imx_pin_reg *pin_reg;
pin_reg           270 drivers/pinctrl/freescale/pinctrl-imx7ulp.c 	pin_reg = &ipctl->pin_regs[offset];
pin_reg           271 drivers/pinctrl/freescale/pinctrl-imx7ulp.c 	if (pin_reg->mux_reg == -1)
pin_reg           274 drivers/pinctrl/freescale/pinctrl-imx7ulp.c 	reg = readl(ipctl->base + pin_reg->mux_reg);
pin_reg           279 drivers/pinctrl/freescale/pinctrl-imx7ulp.c 	writel(reg, ipctl->base + pin_reg->mux_reg);
pin_reg           298 drivers/pinctrl/freescale/pinctrl-vf610.c 	const struct imx_pin_reg *pin_reg;
pin_reg           301 drivers/pinctrl/freescale/pinctrl-vf610.c 	pin_reg = &ipctl->pin_regs[offset];
pin_reg           302 drivers/pinctrl/freescale/pinctrl-vf610.c 	if (pin_reg->mux_reg == -1)
pin_reg           306 drivers/pinctrl/freescale/pinctrl-vf610.c 	reg = readl(ipctl->base + pin_reg->mux_reg);
pin_reg           311 drivers/pinctrl/freescale/pinctrl-vf610.c 	writel(reg, ipctl->base + pin_reg->mux_reg);
pin_reg            42 drivers/pinctrl/pinctrl-amd.c 	u32 pin_reg;
pin_reg            46 drivers/pinctrl/pinctrl-amd.c 	pin_reg = readl(gpio_dev->base + offset * 4);
pin_reg            49 drivers/pinctrl/pinctrl-amd.c 	return !(pin_reg & BIT(OUTPUT_ENABLE_OFF));
pin_reg            55 drivers/pinctrl/pinctrl-amd.c 	u32 pin_reg;
pin_reg            59 drivers/pinctrl/pinctrl-amd.c 	pin_reg = readl(gpio_dev->base + offset * 4);
pin_reg            60 drivers/pinctrl/pinctrl-amd.c 	pin_reg &= ~BIT(OUTPUT_ENABLE_OFF);
pin_reg            61 drivers/pinctrl/pinctrl-amd.c 	writel(pin_reg, gpio_dev->base + offset * 4);
pin_reg            70 drivers/pinctrl/pinctrl-amd.c 	u32 pin_reg;
pin_reg            75 drivers/pinctrl/pinctrl-amd.c 	pin_reg = readl(gpio_dev->base + offset * 4);
pin_reg            76 drivers/pinctrl/pinctrl-amd.c 	pin_reg |= BIT(OUTPUT_ENABLE_OFF);
pin_reg            78 drivers/pinctrl/pinctrl-amd.c 		pin_reg |= BIT(OUTPUT_VALUE_OFF);
pin_reg            80 drivers/pinctrl/pinctrl-amd.c 		pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
pin_reg            81 drivers/pinctrl/pinctrl-amd.c 	writel(pin_reg, gpio_dev->base + offset * 4);
pin_reg            89 drivers/pinctrl/pinctrl-amd.c 	u32 pin_reg;
pin_reg            94 drivers/pinctrl/pinctrl-amd.c 	pin_reg = readl(gpio_dev->base + offset * 4);
pin_reg            97 drivers/pinctrl/pinctrl-amd.c 	return !!(pin_reg & BIT(PIN_STS_OFF));
pin_reg           102 drivers/pinctrl/pinctrl-amd.c 	u32 pin_reg;
pin_reg           107 drivers/pinctrl/pinctrl-amd.c 	pin_reg = readl(gpio_dev->base + offset * 4);
pin_reg           109 drivers/pinctrl/pinctrl-amd.c 		pin_reg |= BIT(OUTPUT_VALUE_OFF);
pin_reg           111 drivers/pinctrl/pinctrl-amd.c 		pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
pin_reg           112 drivers/pinctrl/pinctrl-amd.c 	writel(pin_reg, gpio_dev->base + offset * 4);
pin_reg           120 drivers/pinctrl/pinctrl-amd.c 	u32 pin_reg;
pin_reg           126 drivers/pinctrl/pinctrl-amd.c 	pin_reg = readl(gpio_dev->base + offset * 4);
pin_reg           129 drivers/pinctrl/pinctrl-amd.c 		pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
pin_reg           130 drivers/pinctrl/pinctrl-amd.c 		pin_reg &= ~DB_TMR_OUT_MASK;
pin_reg           142 drivers/pinctrl/pinctrl-amd.c 			pin_reg |= 1;
pin_reg           143 drivers/pinctrl/pinctrl-amd.c 			pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
pin_reg           144 drivers/pinctrl/pinctrl-amd.c 			pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
pin_reg           147 drivers/pinctrl/pinctrl-amd.c 			pin_reg |= time & DB_TMR_OUT_MASK;
pin_reg           148 drivers/pinctrl/pinctrl-amd.c 			pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
pin_reg           149 drivers/pinctrl/pinctrl-amd.c 			pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
pin_reg           152 drivers/pinctrl/pinctrl-amd.c 			pin_reg |= time & DB_TMR_OUT_MASK;
pin_reg           153 drivers/pinctrl/pinctrl-amd.c 			pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
pin_reg           154 drivers/pinctrl/pinctrl-amd.c 			pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
pin_reg           157 drivers/pinctrl/pinctrl-amd.c 			pin_reg |= time & DB_TMR_OUT_MASK;
pin_reg           158 drivers/pinctrl/pinctrl-amd.c 			pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
pin_reg           159 drivers/pinctrl/pinctrl-amd.c 			pin_reg |= BIT(DB_TMR_LARGE_OFF);
pin_reg           162 drivers/pinctrl/pinctrl-amd.c 			pin_reg |= time & DB_TMR_OUT_MASK;
pin_reg           163 drivers/pinctrl/pinctrl-amd.c 			pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
pin_reg           164 drivers/pinctrl/pinctrl-amd.c 			pin_reg |= BIT(DB_TMR_LARGE_OFF);
pin_reg           166 drivers/pinctrl/pinctrl-amd.c 			pin_reg &= ~DB_CNTRl_MASK;
pin_reg           170 drivers/pinctrl/pinctrl-amd.c 		pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
pin_reg           171 drivers/pinctrl/pinctrl-amd.c 		pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
pin_reg           172 drivers/pinctrl/pinctrl-amd.c 		pin_reg &= ~DB_TMR_OUT_MASK;
pin_reg           173 drivers/pinctrl/pinctrl-amd.c 		pin_reg &= ~DB_CNTRl_MASK;
pin_reg           175 drivers/pinctrl/pinctrl-amd.c 	writel(pin_reg, gpio_dev->base + offset * 4);
pin_reg           196 drivers/pinctrl/pinctrl-amd.c 	u32 pin_reg;
pin_reg           242 drivers/pinctrl/pinctrl-amd.c 			pin_reg = readl(gpio_dev->base + i * 4);
pin_reg           245 drivers/pinctrl/pinctrl-amd.c 			if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) {
pin_reg           246 drivers/pinctrl/pinctrl-amd.c 				u8 level = (pin_reg >> ACTIVE_LEVEL_OFF) &
pin_reg           254 drivers/pinctrl/pinctrl-amd.c 				else if (!(pin_reg & BIT(LEVEL_TRIG_OFF)) &&
pin_reg           260 drivers/pinctrl/pinctrl-amd.c 				if (pin_reg & BIT(LEVEL_TRIG_OFF))
pin_reg           272 drivers/pinctrl/pinctrl-amd.c 			if (pin_reg & BIT(INTERRUPT_MASK_OFF))
pin_reg           279 drivers/pinctrl/pinctrl-amd.c 			if (pin_reg & BIT(WAKE_CNTRL_OFF_S0I3))
pin_reg           284 drivers/pinctrl/pinctrl-amd.c 			if (pin_reg & BIT(WAKE_CNTRL_OFF_S3))
pin_reg           289 drivers/pinctrl/pinctrl-amd.c 			if (pin_reg & BIT(WAKE_CNTRL_OFF_S4))
pin_reg           294 drivers/pinctrl/pinctrl-amd.c 			if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) {
pin_reg           296 drivers/pinctrl/pinctrl-amd.c 				if (pin_reg & BIT(PULL_UP_SEL_OFF))
pin_reg           305 drivers/pinctrl/pinctrl-amd.c 			if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF))
pin_reg           310 drivers/pinctrl/pinctrl-amd.c 			if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) {
pin_reg           313 drivers/pinctrl/pinctrl-amd.c 				if (pin_reg & BIT(OUTPUT_VALUE_OFF))
pin_reg           321 drivers/pinctrl/pinctrl-amd.c 				if (pin_reg & BIT(PIN_STS_OFF))
pin_reg           333 drivers/pinctrl/pinctrl-amd.c 				output_value, output_enable, pin_reg);
pin_reg           343 drivers/pinctrl/pinctrl-amd.c 	u32 pin_reg;
pin_reg           349 drivers/pinctrl/pinctrl-amd.c 	pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
pin_reg           350 drivers/pinctrl/pinctrl-amd.c 	pin_reg |= BIT(INTERRUPT_ENABLE_OFF);
pin_reg           351 drivers/pinctrl/pinctrl-amd.c 	pin_reg |= BIT(INTERRUPT_MASK_OFF);
pin_reg           352 drivers/pinctrl/pinctrl-amd.c 	writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
pin_reg           358 drivers/pinctrl/pinctrl-amd.c 	u32 pin_reg;
pin_reg           364 drivers/pinctrl/pinctrl-amd.c 	pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
pin_reg           365 drivers/pinctrl/pinctrl-amd.c 	pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF);
pin_reg           366 drivers/pinctrl/pinctrl-amd.c 	pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
pin_reg           367 drivers/pinctrl/pinctrl-amd.c 	writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
pin_reg           373 drivers/pinctrl/pinctrl-amd.c 	u32 pin_reg;
pin_reg           379 drivers/pinctrl/pinctrl-amd.c 	pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
pin_reg           380 drivers/pinctrl/pinctrl-amd.c 	pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
pin_reg           381 drivers/pinctrl/pinctrl-amd.c 	writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
pin_reg           387 drivers/pinctrl/pinctrl-amd.c 	u32 pin_reg;
pin_reg           393 drivers/pinctrl/pinctrl-amd.c 	pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
pin_reg           394 drivers/pinctrl/pinctrl-amd.c 	pin_reg |= BIT(INTERRUPT_MASK_OFF);
pin_reg           395 drivers/pinctrl/pinctrl-amd.c 	writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
pin_reg           416 drivers/pinctrl/pinctrl-amd.c 	u32 pin_reg, pin_reg_irq_en, mask;
pin_reg           422 drivers/pinctrl/pinctrl-amd.c 	pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
pin_reg           435 drivers/pinctrl/pinctrl-amd.c 		pin_reg &= ~BIT(LEVEL_TRIG_OFF);
pin_reg           436 drivers/pinctrl/pinctrl-amd.c 		pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
pin_reg           437 drivers/pinctrl/pinctrl-amd.c 		pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
pin_reg           438 drivers/pinctrl/pinctrl-amd.c 		pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
pin_reg           443 drivers/pinctrl/pinctrl-amd.c 		pin_reg &= ~BIT(LEVEL_TRIG_OFF);
pin_reg           444 drivers/pinctrl/pinctrl-amd.c 		pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
pin_reg           445 drivers/pinctrl/pinctrl-amd.c 		pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
pin_reg           446 drivers/pinctrl/pinctrl-amd.c 		pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
pin_reg           451 drivers/pinctrl/pinctrl-amd.c 		pin_reg &= ~BIT(LEVEL_TRIG_OFF);
pin_reg           452 drivers/pinctrl/pinctrl-amd.c 		pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
pin_reg           453 drivers/pinctrl/pinctrl-amd.c 		pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF;
pin_reg           454 drivers/pinctrl/pinctrl-amd.c 		pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
pin_reg           459 drivers/pinctrl/pinctrl-amd.c 		pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
pin_reg           460 drivers/pinctrl/pinctrl-amd.c 		pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
pin_reg           461 drivers/pinctrl/pinctrl-amd.c 		pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
pin_reg           462 drivers/pinctrl/pinctrl-amd.c 		pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
pin_reg           463 drivers/pinctrl/pinctrl-amd.c 		pin_reg |= DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF;
pin_reg           468 drivers/pinctrl/pinctrl-amd.c 		pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
pin_reg           469 drivers/pinctrl/pinctrl-amd.c 		pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
pin_reg           470 drivers/pinctrl/pinctrl-amd.c 		pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
pin_reg           471 drivers/pinctrl/pinctrl-amd.c 		pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
pin_reg           472 drivers/pinctrl/pinctrl-amd.c 		pin_reg |= DB_TYPE_PRESERVE_HIGH_GLITCH << DB_CNTRL_OFF;
pin_reg           484 drivers/pinctrl/pinctrl-amd.c 	pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF;
pin_reg           501 drivers/pinctrl/pinctrl-amd.c 	pin_reg_irq_en = pin_reg;
pin_reg           507 drivers/pinctrl/pinctrl-amd.c 	writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
pin_reg           645 drivers/pinctrl/pinctrl-amd.c 	u32 pin_reg;
pin_reg           652 drivers/pinctrl/pinctrl-amd.c 	pin_reg = readl(gpio_dev->base + pin*4);
pin_reg           656 drivers/pinctrl/pinctrl-amd.c 		arg = pin_reg & DB_TMR_OUT_MASK;
pin_reg           660 drivers/pinctrl/pinctrl-amd.c 		arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0);
pin_reg           664 drivers/pinctrl/pinctrl-amd.c 		arg = (pin_reg >> PULL_UP_SEL_OFF) & (BIT(0) | BIT(1));
pin_reg           668 drivers/pinctrl/pinctrl-amd.c 		arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK;
pin_reg           688 drivers/pinctrl/pinctrl-amd.c 	u32 pin_reg;
pin_reg           697 drivers/pinctrl/pinctrl-amd.c 		pin_reg = readl(gpio_dev->base + pin*4);
pin_reg           701 drivers/pinctrl/pinctrl-amd.c 			pin_reg &= ~DB_TMR_OUT_MASK;
pin_reg           702 drivers/pinctrl/pinctrl-amd.c 			pin_reg |= arg & DB_TMR_OUT_MASK;
pin_reg           706 drivers/pinctrl/pinctrl-amd.c 			pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF);
pin_reg           707 drivers/pinctrl/pinctrl-amd.c 			pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF;
pin_reg           711 drivers/pinctrl/pinctrl-amd.c 			pin_reg &= ~BIT(PULL_UP_SEL_OFF);
pin_reg           712 drivers/pinctrl/pinctrl-amd.c 			pin_reg |= (arg & BIT(0)) << PULL_UP_SEL_OFF;
pin_reg           713 drivers/pinctrl/pinctrl-amd.c 			pin_reg &= ~BIT(PULL_UP_ENABLE_OFF);
pin_reg           714 drivers/pinctrl/pinctrl-amd.c 			pin_reg |= ((arg>>1) & BIT(0)) << PULL_UP_ENABLE_OFF;
pin_reg           718 drivers/pinctrl/pinctrl-amd.c 			pin_reg &= ~(DRV_STRENGTH_SEL_MASK
pin_reg           720 drivers/pinctrl/pinctrl-amd.c 			pin_reg |= (arg & DRV_STRENGTH_SEL_MASK)
pin_reg           730 drivers/pinctrl/pinctrl-amd.c 		writel(pin_reg, gpio_dev->base + pin*4);