pin_pol          1099 drivers/gpu/drm/rockchip/rockchip_drm_vop.c 	uint32_t pin_pol, val;
pin_pol          1120 drivers/gpu/drm/rockchip/rockchip_drm_vop.c 	pin_pol = BIT(DCLK_INVERT);
pin_pol          1121 drivers/gpu/drm/rockchip/rockchip_drm_vop.c 	pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) ?
pin_pol          1123 drivers/gpu/drm/rockchip/rockchip_drm_vop.c 	pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) ?
pin_pol          1125 drivers/gpu/drm/rockchip/rockchip_drm_vop.c 	VOP_REG_SET(vop, output, pin_pol, pin_pol);
pin_pol          1131 drivers/gpu/drm/rockchip/rockchip_drm_vop.c 		VOP_REG_SET(vop, output, rgb_pin_pol, pin_pol);
pin_pol          1134 drivers/gpu/drm/rockchip/rockchip_drm_vop.c 		VOP_REG_SET(vop, output, edp_pin_pol, pin_pol);
pin_pol          1138 drivers/gpu/drm/rockchip/rockchip_drm_vop.c 		VOP_REG_SET(vop, output, hdmi_pin_pol, pin_pol);
pin_pol          1142 drivers/gpu/drm/rockchip/rockchip_drm_vop.c 		VOP_REG_SET(vop, output, mipi_pin_pol, pin_pol);
pin_pol          1148 drivers/gpu/drm/rockchip/rockchip_drm_vop.c 		pin_pol &= ~BIT(DCLK_INVERT);
pin_pol          1149 drivers/gpu/drm/rockchip/rockchip_drm_vop.c 		VOP_REG_SET(vop, output, dp_pin_pol, pin_pol);
pin_pol            47 drivers/gpu/drm/rockchip/rockchip_drm_vop.h 	struct vop_reg pin_pol;
pin_pol           130 drivers/gpu/drm/rockchip/rockchip_vop_reg.c 	.pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4),
pin_pol           364 drivers/gpu/drm/rockchip/rockchip_vop_reg.c 	.pin_pol = VOP_REG(RK3066_DSP_CTRL0, 0x7, 4),
pin_pol           458 drivers/gpu/drm/rockchip/rockchip_vop_reg.c 	.pin_pol = VOP_REG(RK3188_DSP_CTRL0, 0xf, 4),
pin_pol           585 drivers/gpu/drm/rockchip/rockchip_vop_reg.c 	.pin_pol = VOP_REG(RK3288_DSP_CTRL0, 0xf, 4),