pin_mask 555 arch/powerpc/platforms/8xx/cpm1.c u16 pin_mask; pin_mask 557 arch/powerpc/platforms/8xx/cpm1.c pin_mask = 1 << (15 - gpio); pin_mask 559 arch/powerpc/platforms/8xx/cpm1.c return !!(in_be16(&iop->dat) & pin_mask); pin_mask 562 arch/powerpc/platforms/8xx/cpm1.c static void __cpm1_gpio16_set(struct of_mm_gpio_chip *mm_gc, u16 pin_mask, pin_mask 569 arch/powerpc/platforms/8xx/cpm1.c cpm1_gc->cpdata |= pin_mask; pin_mask 571 arch/powerpc/platforms/8xx/cpm1.c cpm1_gc->cpdata &= ~pin_mask; pin_mask 581 arch/powerpc/platforms/8xx/cpm1.c u16 pin_mask = 1 << (15 - gpio); pin_mask 585 arch/powerpc/platforms/8xx/cpm1.c __cpm1_gpio16_set(mm_gc, pin_mask, value); pin_mask 604 arch/powerpc/platforms/8xx/cpm1.c u16 pin_mask = 1 << (15 - gpio); pin_mask 608 arch/powerpc/platforms/8xx/cpm1.c setbits16(&iop->dir, pin_mask); pin_mask 609 arch/powerpc/platforms/8xx/cpm1.c __cpm1_gpio16_set(mm_gc, pin_mask, val); pin_mask 622 arch/powerpc/platforms/8xx/cpm1.c u16 pin_mask = 1 << (15 - gpio); pin_mask 626 arch/powerpc/platforms/8xx/cpm1.c clrbits16(&iop->dir, pin_mask); pin_mask 692 arch/powerpc/platforms/8xx/cpm1.c u32 pin_mask; pin_mask 694 arch/powerpc/platforms/8xx/cpm1.c pin_mask = 1 << (31 - gpio); pin_mask 696 arch/powerpc/platforms/8xx/cpm1.c return !!(in_be32(&iop->dat) & pin_mask); pin_mask 699 arch/powerpc/platforms/8xx/cpm1.c static void __cpm1_gpio32_set(struct of_mm_gpio_chip *mm_gc, u32 pin_mask, pin_mask 706 arch/powerpc/platforms/8xx/cpm1.c cpm1_gc->cpdata |= pin_mask; pin_mask 708 arch/powerpc/platforms/8xx/cpm1.c cpm1_gc->cpdata &= ~pin_mask; pin_mask 718 arch/powerpc/platforms/8xx/cpm1.c u32 pin_mask = 1 << (31 - gpio); pin_mask 722 arch/powerpc/platforms/8xx/cpm1.c __cpm1_gpio32_set(mm_gc, pin_mask, value); pin_mask 733 arch/powerpc/platforms/8xx/cpm1.c u32 pin_mask = 1 << (31 - gpio); pin_mask 737 arch/powerpc/platforms/8xx/cpm1.c setbits32(&iop->dir, pin_mask); pin_mask 738 arch/powerpc/platforms/8xx/cpm1.c __cpm1_gpio32_set(mm_gc, pin_mask, val); pin_mask 751 arch/powerpc/platforms/8xx/cpm1.c u32 pin_mask = 1 << (31 - gpio); pin_mask 755 arch/powerpc/platforms/8xx/cpm1.c clrbits32(&iop->dir, pin_mask); pin_mask 120 arch/powerpc/sysdev/cpm_common.c u32 pin_mask; pin_mask 122 arch/powerpc/sysdev/cpm_common.c pin_mask = 1 << (31 - gpio); pin_mask 124 arch/powerpc/sysdev/cpm_common.c return !!(in_be32(&iop->dat) & pin_mask); pin_mask 127 arch/powerpc/sysdev/cpm_common.c static void __cpm2_gpio32_set(struct of_mm_gpio_chip *mm_gc, u32 pin_mask, pin_mask 134 arch/powerpc/sysdev/cpm_common.c cpm2_gc->cpdata |= pin_mask; pin_mask 136 arch/powerpc/sysdev/cpm_common.c cpm2_gc->cpdata &= ~pin_mask; pin_mask 146 arch/powerpc/sysdev/cpm_common.c u32 pin_mask = 1 << (31 - gpio); pin_mask 150 arch/powerpc/sysdev/cpm_common.c __cpm2_gpio32_set(mm_gc, pin_mask, value); pin_mask 161 arch/powerpc/sysdev/cpm_common.c u32 pin_mask = 1 << (31 - gpio); pin_mask 165 arch/powerpc/sysdev/cpm_common.c setbits32(&iop->dir, pin_mask); pin_mask 166 arch/powerpc/sysdev/cpm_common.c __cpm2_gpio32_set(mm_gc, pin_mask, val); pin_mask 179 arch/powerpc/sysdev/cpm_common.c u32 pin_mask = 1 << (31 - gpio); pin_mask 183 arch/powerpc/sysdev/cpm_common.c clrbits32(&iop->dir, pin_mask); pin_mask 73 drivers/gpio/gpio-mxs.c u32 pin_mask = 1 << d->hwirq; pin_mask 84 drivers/gpio/gpio-mxs.c port->both_edges &= ~pin_mask; pin_mask 87 drivers/gpio/gpio-mxs.c val = readl(port->base + PINCTRL_DIN(port)) & pin_mask; pin_mask 92 drivers/gpio/gpio-mxs.c port->both_edges |= pin_mask; pin_mask 113 drivers/gpio/gpio-mxs.c writel(pin_mask, pin_addr + MXS_SET); pin_mask 114 drivers/gpio/gpio-mxs.c writel(pin_mask, port->base + PINCTRL_IRQEN(port) + MXS_SET); pin_mask 116 drivers/gpio/gpio-mxs.c writel(pin_mask, pin_addr + MXS_CLR); pin_mask 117 drivers/gpio/gpio-mxs.c writel(pin_mask, port->base + PINCTRL_PIN2IRQ(port) + MXS_SET); pin_mask 123 drivers/gpio/gpio-mxs.c writel(pin_mask, pin_addr + MXS_SET); pin_mask 125 drivers/gpio/gpio-mxs.c writel(pin_mask, pin_addr + MXS_CLR); pin_mask 127 drivers/gpio/gpio-mxs.c writel(pin_mask, port->base + PINCTRL_IRQSTAT(port) + MXS_CLR); pin_mask 209 drivers/gpio/gpio-tegra.c u32 pin_mask = BIT(GPIO_BIT(offset)); pin_mask 213 drivers/gpio/gpio-tegra.c if (!(cnf & pin_mask)) pin_mask 218 drivers/gpio/gpio-tegra.c return !(oe & pin_mask); pin_mask 450 drivers/gpu/drm/i915/display/intel_hotplug.c u32 pin_mask, u32 long_mask) pin_mask 459 drivers/gpu/drm/i915/display/intel_hotplug.c if (!pin_mask) pin_mask 476 drivers/gpu/drm/i915/display/intel_hotplug.c if (!(BIT(pin) & pin_mask)) pin_mask 501 drivers/gpu/drm/i915/display/intel_hotplug.c if (!(BIT(pin) & pin_mask)) pin_mask 22 drivers/gpu/drm/i915/display/intel_hotplug.h u32 pin_mask, u32 long_mask); pin_mask 1536 drivers/gpu/drm/i915/i915_irq.c u32 *pin_mask, u32 *long_mask, pin_mask 1543 drivers/gpu/drm/i915/i915_irq.c BUILD_BUG_ON(BITS_PER_TYPE(*pin_mask) < HPD_NUM_PINS); pin_mask 1549 drivers/gpu/drm/i915/i915_irq.c *pin_mask |= BIT(pin); pin_mask 1556 drivers/gpu/drm/i915/i915_irq.c hotplug_trigger, dig_hotplug_reg, *pin_mask, *long_mask); pin_mask 1910 drivers/gpu/drm/i915/i915_irq.c u32 pin_mask = 0, long_mask = 0; pin_mask 1917 drivers/gpu/drm/i915/i915_irq.c intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, pin_mask 1922 drivers/gpu/drm/i915/i915_irq.c intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); pin_mask 1931 drivers/gpu/drm/i915/i915_irq.c intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, pin_mask 1935 drivers/gpu/drm/i915/i915_irq.c intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); pin_mask 2109 drivers/gpu/drm/i915/i915_irq.c u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0; pin_mask 2130 drivers/gpu/drm/i915/i915_irq.c intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, hotplug_trigger, pin_mask 2134 drivers/gpu/drm/i915/i915_irq.c intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); pin_mask 2264 drivers/gpu/drm/i915/i915_irq.c u32 pin_mask = 0, long_mask = 0; pin_mask 2280 drivers/gpu/drm/i915/i915_irq.c intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, pin_mask 2292 drivers/gpu/drm/i915/i915_irq.c intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, pin_mask 2298 drivers/gpu/drm/i915/i915_irq.c if (pin_mask) pin_mask 2299 drivers/gpu/drm/i915/i915_irq.c intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); pin_mask 2309 drivers/gpu/drm/i915/i915_irq.c u32 pin_mask = 0, long_mask = 0; pin_mask 2317 drivers/gpu/drm/i915/i915_irq.c intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, pin_mask 2329 drivers/gpu/drm/i915/i915_irq.c intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, pin_mask 2335 drivers/gpu/drm/i915/i915_irq.c if (pin_mask) pin_mask 2336 drivers/gpu/drm/i915/i915_irq.c intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); pin_mask 2347 drivers/gpu/drm/i915/i915_irq.c u32 pin_mask = 0, long_mask = 0; pin_mask 2355 drivers/gpu/drm/i915/i915_irq.c intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, pin_mask 2366 drivers/gpu/drm/i915/i915_irq.c intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, pin_mask 2371 drivers/gpu/drm/i915/i915_irq.c if (pin_mask) pin_mask 2372 drivers/gpu/drm/i915/i915_irq.c intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); pin_mask 2382 drivers/gpu/drm/i915/i915_irq.c u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0; pin_mask 2387 drivers/gpu/drm/i915/i915_irq.c intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, hotplug_trigger, pin_mask 2391 drivers/gpu/drm/i915/i915_irq.c intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); pin_mask 2560 drivers/gpu/drm/i915/i915_irq.c u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0; pin_mask 2565 drivers/gpu/drm/i915/i915_irq.c intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, hotplug_trigger, pin_mask 2569 drivers/gpu/drm/i915/i915_irq.c intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); pin_mask 2574 drivers/gpu/drm/i915/i915_irq.c u32 pin_mask = 0, long_mask = 0; pin_mask 2594 drivers/gpu/drm/i915/i915_irq.c intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, trigger_tc, pin_mask 2604 drivers/gpu/drm/i915/i915_irq.c intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, trigger_tbt, pin_mask 2608 drivers/gpu/drm/i915/i915_irq.c if (pin_mask) pin_mask 2609 drivers/gpu/drm/i915/i915_irq.c intel_hpd_irq_handler(dev_priv, pin_mask, long_mask); pin_mask 487 drivers/gpu/drm/nouveau/dispnv04/tvmodesnv17.c if (tv_enc->pin_mask & 0x4) pin_mask 489 drivers/gpu/drm/nouveau/dispnv04/tvmodesnv17.c else if (tv_enc->pin_mask & 0x2) pin_mask 130 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c get_tv_detect_quirks(struct drm_device *dev, uint32_t *pin_mask) pin_mask 136 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c *pin_mask = device->quirk->tv_pin_mask; pin_mask 151 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c bool reliable = get_tv_detect_quirks(dev, &tv_enc->pin_mask); pin_mask 159 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c tv_enc->pin_mask = pin_mask 162 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c tv_enc->pin_mask = pin_mask 166 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c switch (tv_enc->pin_mask) { pin_mask 807 drivers/gpu/drm/nouveau/dispnv04/tvnv17.c tv_enc->pin_mask = 0; pin_mask 83 drivers/gpu/drm/nouveau/dispnv04/tvnv17.h uint32_t pin_mask; pin_mask 1092 drivers/pinctrl/pinctrl-st.c u32 pin_mask = pc->rt_pin_mask; pin_mask 1095 drivers/pinctrl/pinctrl-st.c if (BIT(j) & pin_mask) { pin_mask 57 drivers/soc/fsl/qe/gpio.c u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio); pin_mask 59 drivers/soc/fsl/qe/gpio.c return !!(in_be32(®s->cpdata) & pin_mask); pin_mask 68 drivers/soc/fsl/qe/gpio.c u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio); pin_mask 73 drivers/soc/fsl/qe/gpio.c qe_gc->cpdata |= pin_mask; pin_mask 75 drivers/soc/fsl/qe/gpio.c qe_gc->cpdata &= ~pin_mask; pin_mask 127 drivers/soc/fsl/qe/qe_io.c u32 pin_mask, tmp_val; pin_mask 134 drivers/soc/fsl/qe/qe_io.c pin_mask = (u32) (1 << (QE_PIO_PINS - 1 - pin)); pin_mask 139 drivers/soc/fsl/qe/qe_io.c out_be32(&par_io[port].cpdata, ~pin_mask & tmp_val); pin_mask 141 drivers/soc/fsl/qe/qe_io.c out_be32(&par_io[port].cpdata, pin_mask | tmp_val);