pic_width         399 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 		dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt;
pic_width         416 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 		dsc_cfg.pic_width *= opp_cnt;
pic_width         500 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 		dsc_cfg.pic_width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right;
pic_width         169 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	if (dsc_cfg->pic_width > dsc20->max_image_width)
pic_width         268 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	DC_LOG_DSC("\tpic_width %d", pps->pic_width);
pic_width         316 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	ASSERT(dsc_cfg->pic_width);
pic_width         327 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 		!dsc_cfg->pic_width || !dsc_cfg->pic_height ||
pic_width         345 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	dsc_reg_vals->pps.pic_width = dsc_cfg->pic_width;
pic_width         354 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	dsc_reg_vals->pps.slice_width = dsc_cfg->pic_width / dsc_cfg->dc_dsc_cfg.num_slices_h;
pic_width         474 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	reg_vals->pps.pic_width                   = 0;
pic_width         533 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 		PIC_WIDTH, reg_vals->pps.pic_width,
pic_width         575 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 		PIC_WIDTH, reg_vals->pps.pic_width,
pic_width        2272 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left
pic_width         521 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	int pic_width;
pic_width         532 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	pic_width = timing->h_addressable + timing->h_border_left + timing->h_border_right;
pic_width         538 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	if (dsc_sink_caps->branch_max_line_width && dsc_sink_caps->branch_max_line_width < pic_width)
pic_width         618 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 		if (pic_width % max_slices_h == 0)
pic_width         628 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	min_slices_h = pic_width / dsc_common_caps.max_slice_width;
pic_width         629 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	if (pic_width % dsc_common_caps.max_slice_width)
pic_width         642 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	if (pic_width % min_slices_h != 0)
pic_width         675 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	slice_width = pic_width / num_slices_h;
pic_width          43 drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c 	to->pic_width                = from->pic_width;
pic_width          35 drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h 	uint32_t pic_width;
pic_width         116 drivers/gpu/drm/drm_dsc.c 	pps_payload->pic_width = cpu_to_be16(dsc_cfg->pic_width);
pic_width         332 drivers/gpu/drm/i915/display/intel_vdsc.c 	vdsc_cfg->pic_width = pipe_config->base.adjusted_mode.crtc_hdisplay;
pic_width         334 drivers/gpu/drm/i915/display/intel_vdsc.c 	vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
pic_width         548 drivers/gpu/drm/i915/display/intel_vdsc.c 		DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances);
pic_width         732 drivers/gpu/drm/i915/display/intel_vdsc.c 		DSC_SLICE_PER_LINE((vdsc_cfg->pic_width / num_vdsc_instances) /
pic_width        11285 drivers/gpu/drm/i915/i915_reg.h #define  DSC_PIC_WIDTH(pic_width)	((pic_width) << 16)
pic_width         110 include/drm/drm_dsc.h 	u16 pic_width;
pic_width         347 include/drm/drm_dsc.h 	__be16 pic_width;