pic_height        400 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 		dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom;
pic_height        501 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 		dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom;
pic_height        267 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	DC_LOG_DSC("\tpic_height %d", pps->pic_height);
pic_height        317 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	ASSERT(dsc_cfg->pic_height);
pic_height        327 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 		!dsc_cfg->pic_width || !dsc_cfg->pic_height ||
pic_height        346 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	dsc_reg_vals->pps.pic_height = dsc_cfg->pic_height;
pic_height        355 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	dsc_reg_vals->pps.slice_height = dsc_cfg->pic_height / dsc_cfg->dc_dsc_cfg.num_slices_v;
pic_height        357 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	ASSERT(dsc_reg_vals->pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height);
pic_height        358 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	if (!(dsc_reg_vals->pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height)) {
pic_height        359 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 		dm_output_to_console("%s: pix height %d not divisible by num_slices_v %d\n\n", __func__, dsc_cfg->pic_height, dsc_cfg->dc_dsc_cfg.num_slices_v);
pic_height        475 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	reg_vals->pps.pic_height                  = 0;
pic_height        534 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 		PIC_HEIGHT, reg_vals->pps.pic_height);
pic_height        576 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 		PIC_HEIGHT, reg_vals->pps.pic_height);
pic_height       2274 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 		dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top
pic_height        527 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	int pic_height;
pic_height        533 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	pic_height = timing->v_addressable + timing->v_border_top + timing->v_border_bottom;
pic_height        683 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	slice_height = min(dsc_policy.min_sice_height, pic_height);
pic_height        685 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	while (slice_height < pic_height && (pic_height % slice_height != 0 ||
pic_height        695 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 	dsc_cfg->num_slices_v = pic_height/slice_height;
pic_height         44 drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c 	to->pic_height               = from->pic_height;
pic_height         36 drivers/gpu/drm/amd/display/dc/inc/hw/dsc.h 	uint32_t pic_height;
pic_height        113 drivers/gpu/drm/drm_dsc.c 	pps_payload->pic_height = cpu_to_be16(dsc_cfg->pic_height);
pic_height        333 drivers/gpu/drm/i915/display/intel_vdsc.c 	vdsc_cfg->pic_height = pipe_config->base.adjusted_mode.crtc_vdisplay;
pic_height        341 drivers/gpu/drm/i915/display/intel_vdsc.c 	if (vdsc_cfg->pic_height % 8 == 0)
pic_height        343 drivers/gpu/drm/i915/display/intel_vdsc.c 	else if (vdsc_cfg->pic_height % 4 == 0)
pic_height        547 drivers/gpu/drm/i915/display/intel_vdsc.c 	pps_val |= DSC_PIC_HEIGHT(vdsc_cfg->pic_height) |
pic_height        734 drivers/gpu/drm/i915/display/intel_vdsc.c 		DSC_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height /
pic_height       11286 drivers/gpu/drm/i915/i915_reg.h #define  DSC_PIC_HEIGHT(pic_height)	((pic_height) << 0)
pic_height        114 include/drm/drm_dsc.h 	u16 pic_height;
pic_height        341 include/drm/drm_dsc.h 	__be16 pic_height;