phys_params      2043 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 	struct dpu_enc_phys_init_params phys_params;
phys_params      2053 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 	memset(&phys_params, 0, sizeof(phys_params));
phys_params      2054 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 	phys_params.dpu_kms = dpu_kms;
phys_params      2055 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 	phys_params.parent = &dpu_enc->base;
phys_params      2056 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 	phys_params.parent_ops = &dpu_encoder_parent_ops;
phys_params      2057 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 	phys_params.enc_spinlock = &dpu_enc->enc_spinlock;
phys_params      2090 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 				phys_params.split_role = ENC_ROLE_MASTER;
phys_params      2092 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 				phys_params.split_role = ENC_ROLE_SLAVE;
phys_params      2094 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 			phys_params.split_role = ENC_ROLE_SOLO;
phys_params      2098 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 				i, controller_id, phys_params.split_role);
phys_params      2100 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 		phys_params.intf_idx = dpu_encoder_get_intf(dpu_kms->catalog,
phys_params      2103 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 		if (phys_params.intf_idx == INTF_MAX) {
phys_params      2112 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 												 &phys_params);