phys_enc 212 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c void dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys *phys_enc, phys_enc 216 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c DRMID(phys_enc->parent), phys_enc->intf_idx - INTF_0, phys_enc 217 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c phys_enc->hw_pp->idx - PINGPONG_0, intr_idx); phys_enc 219 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c if (phys_enc->parent_ops->handle_frame_done) phys_enc 220 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c phys_enc->parent_ops->handle_frame_done( phys_enc 221 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c phys_enc->parent, phys_enc, phys_enc 228 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc, phys_enc 236 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c if (!phys_enc || !wait_info || intr_idx >= INTR_IDX_MAX) { phys_enc 240 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c irq = &phys_enc->irq[intr_idx]; phys_enc 245 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c if (phys_enc->enable_state == DPU_ENC_DISABLED) { phys_enc 247 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c DRMID(phys_enc->parent), intr_idx, irq->hw_idx, phys_enc 254 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c DRMID(phys_enc->parent), intr_idx, irq->hw_idx, phys_enc 260 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c DRMID(phys_enc->parent), intr_idx, irq->hw_idx, phys_enc 261 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c irq->irq_idx, phys_enc->hw_pp->idx - PINGPONG_0, phys_enc 265 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c DRMID(phys_enc->parent), phys_enc 270 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c irq_status = dpu_core_irq_read(phys_enc->dpu_kms, phys_enc 277 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c DRMID(phys_enc->parent), intr_idx, phys_enc 279 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c phys_enc->hw_pp->idx - PINGPONG_0, phys_enc 282 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c irq->cb.func(phys_enc, irq->irq_idx); phys_enc 289 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c DRMID(phys_enc->parent), intr_idx, phys_enc 291 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c phys_enc->hw_pp->idx - PINGPONG_0, phys_enc 296 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c trace_dpu_enc_irq_wait_success(DRMID(phys_enc->parent), phys_enc 298 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c phys_enc->hw_pp->idx - PINGPONG_0, phys_enc 305 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c int dpu_encoder_helper_register_irq(struct dpu_encoder_phys *phys_enc, phys_enc 311 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c if (!phys_enc || intr_idx >= INTR_IDX_MAX) { phys_enc 315 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c irq = &phys_enc->irq[intr_idx]; phys_enc 318 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c DPU_DEBUG_PHYS(phys_enc, phys_enc 324 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c irq->irq_idx = dpu_core_irq_idx_lookup(phys_enc->dpu_kms, phys_enc 327 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c DPU_ERROR_PHYS(phys_enc, phys_enc 333 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c ret = dpu_core_irq_register_callback(phys_enc->dpu_kms, irq->irq_idx, phys_enc 336 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c DPU_ERROR_PHYS(phys_enc, phys_enc 343 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c ret = dpu_core_irq_enable(phys_enc->dpu_kms, &irq->irq_idx, 1); phys_enc 346 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c DRMID(phys_enc->parent), intr_idx, irq->hw_idx, phys_enc 348 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_core_irq_unregister_callback(phys_enc->dpu_kms, phys_enc 354 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c trace_dpu_enc_irq_register_success(DRMID(phys_enc->parent), intr_idx, phys_enc 360 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c int dpu_encoder_helper_unregister_irq(struct dpu_encoder_phys *phys_enc, phys_enc 366 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c if (!phys_enc) { phys_enc 370 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c irq = &phys_enc->irq[intr_idx]; phys_enc 375 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c DRMID(phys_enc->parent), intr_idx, irq->hw_idx, phys_enc 380 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c ret = dpu_core_irq_disable(phys_enc->dpu_kms, &irq->irq_idx, 1); phys_enc 383 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c DRMID(phys_enc->parent), intr_idx, irq->hw_idx, phys_enc 387 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c ret = dpu_core_irq_unregister_callback(phys_enc->dpu_kms, irq->irq_idx, phys_enc 391 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c DRMID(phys_enc->parent), intr_idx, irq->hw_idx, phys_enc 395 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c trace_dpu_enc_irq_unregister_success(DRMID(phys_enc->parent), intr_idx, phys_enc 459 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c struct dpu_encoder_phys *phys_enc, phys_enc 467 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c if (!phys_enc || !phys_enc->hw_mdptop || !phys_enc->parent) { phys_enc 468 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c DPU_ERROR("invalid arg(s), encoder %d\n", phys_enc != 0); phys_enc 472 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc = to_dpu_encoder_virt(phys_enc->parent); phys_enc 473 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c hw_mdptop = phys_enc->hw_mdptop; phys_enc 485 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c if (phys_enc->split_role == ENC_ROLE_SOLO) { phys_enc 492 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c cfg.mode = phys_enc->intf_mode; phys_enc 495 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c if (cfg.en && phys_enc->ops.needs_single_flush && phys_enc 496 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c phys_enc->ops.needs_single_flush(phys_enc)) phys_enc 499 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c if (phys_enc->split_role == ENC_ROLE_MASTER) { phys_enc 1478 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c void dpu_encoder_helper_trigger_start(struct dpu_encoder_phys *phys_enc) phys_enc 1482 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c if (!phys_enc) { phys_enc 1487 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c ctl = phys_enc->hw_ctl; phys_enc 1490 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c trace_dpu_enc_trigger_start(DRMID(phys_enc->parent), ctl->idx); phys_enc 1519 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c static void dpu_encoder_helper_hw_reset(struct dpu_encoder_phys *phys_enc) phys_enc 1525 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c if (!phys_enc) { phys_enc 1529 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c dpu_enc = to_dpu_encoder_virt(phys_enc->parent); phys_enc 1530 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c ctl = phys_enc->hw_ctl; phys_enc 1535 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c DRM_DEBUG_KMS("id:%u ctl %d reset\n", DRMID(phys_enc->parent), phys_enc 1542 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c phys_enc->enable_state = DPU_ENC_ENABLED; phys_enc 2255 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c int (*fn_wait)(struct dpu_encoder_phys *phys_enc) = NULL; phys_enc 135 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h int (*wait_for_commit_done)(struct dpu_encoder_phys *phys_enc); phys_enc 136 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h int (*wait_for_tx_complete)(struct dpu_encoder_phys *phys_enc); phys_enc 137 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h int (*wait_for_vblank)(struct dpu_encoder_phys *phys_enc); phys_enc 138 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h void (*prepare_for_kickoff)(struct dpu_encoder_phys *phys_enc); phys_enc 139 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h void (*handle_post_kickoff)(struct dpu_encoder_phys *phys_enc); phys_enc 140 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h void (*trigger_start)(struct dpu_encoder_phys *phys_enc); phys_enc 141 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h bool (*needs_single_flush)(struct dpu_encoder_phys *phys_enc); phys_enc 143 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h void (*prepare_idle_pc)(struct dpu_encoder_phys *phys_enc); phys_enc 319 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h void dpu_encoder_helper_trigger_start(struct dpu_encoder_phys *phys_enc); phys_enc 322 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h struct dpu_encoder_phys *phys_enc) phys_enc 326 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h if (!phys_enc || phys_enc->enable_state == DPU_ENC_DISABLING) phys_enc 329 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h dpu_cstate = to_dpu_crtc_state(phys_enc->parent->crtc->state); phys_enc 331 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h if (phys_enc->split_role == ENC_ROLE_SOLO && phys_enc 346 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h struct dpu_encoder_phys *phys_enc, phys_enc 355 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h void dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys *phys_enc, phys_enc 366 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc, phys_enc 376 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h int dpu_encoder_helper_register_irq(struct dpu_encoder_phys *phys_enc, phys_enc 385 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h int dpu_encoder_helper_unregister_irq(struct dpu_encoder_phys *phys_enc, phys_enc 38 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c static bool dpu_encoder_phys_cmd_is_master(struct dpu_encoder_phys *phys_enc) phys_enc 40 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c return (phys_enc->split_role != ENC_ROLE_SLAVE) ? true : false; phys_enc 44 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c struct dpu_encoder_phys *phys_enc, phys_enc 48 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c if (phys_enc) phys_enc 49 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c DPU_DEBUG_CMDENC(to_dpu_encoder_phys_cmd(phys_enc), "\n"); phys_enc 54 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c struct dpu_encoder_phys *phys_enc) phys_enc 57 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c to_dpu_encoder_phys_cmd(phys_enc); phys_enc 61 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c if (!phys_enc) phys_enc 64 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c ctl = phys_enc->hw_ctl; phys_enc 68 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c intf_cfg.intf = phys_enc->intf_idx; phys_enc 71 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc); phys_enc 77 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c struct dpu_encoder_phys *phys_enc = arg; phys_enc 82 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c if (!phys_enc || !phys_enc->hw_pp) phys_enc 87 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c if (phys_enc->parent_ops->handle_frame_done) phys_enc 88 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c phys_enc->parent_ops->handle_frame_done(phys_enc->parent, phys_enc 89 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c phys_enc, event); phys_enc 91 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags); phys_enc 92 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c new_cnt = atomic_add_unless(&phys_enc->pending_kickoff_cnt, -1, 0); phys_enc 93 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags); phys_enc 95 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c trace_dpu_enc_phys_cmd_pp_tx_done(DRMID(phys_enc->parent), phys_enc 96 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c phys_enc->hw_pp->idx - PINGPONG_0, phys_enc 100 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c wake_up_all(&phys_enc->pending_kickoff_wq); phys_enc 106 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c struct dpu_encoder_phys *phys_enc = arg; phys_enc 109 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c if (!phys_enc || !phys_enc->hw_pp) phys_enc 113 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c cmd_enc = to_dpu_encoder_phys_cmd(phys_enc); phys_enc 115 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c if (phys_enc->parent_ops->handle_vblank_virt) phys_enc 116 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c phys_enc->parent_ops->handle_vblank_virt(phys_enc->parent, phys_enc 117 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c phys_enc); phys_enc 126 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c struct dpu_encoder_phys *phys_enc = arg; phys_enc 129 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c if (!phys_enc || !phys_enc->hw_ctl) phys_enc 133 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c cmd_enc = to_dpu_encoder_phys_cmd(phys_enc); phys_enc 135 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c atomic_add_unless(&phys_enc->pending_ctlstart_cnt, -1, 0); phys_enc 138 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c wake_up_all(&phys_enc->pending_kickoff_wq); phys_enc 144 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c struct dpu_encoder_phys *phys_enc = arg; phys_enc 146 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c if (!phys_enc) phys_enc 149 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c if (phys_enc->parent_ops->handle_underrun_virt) phys_enc 150 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c phys_enc->parent_ops->handle_underrun_virt(phys_enc->parent, phys_enc 151 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c phys_enc); phys_enc 155 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c struct dpu_encoder_phys *phys_enc) phys_enc 159 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c irq = &phys_enc->irq[INTR_IDX_CTL_START]; phys_enc 160 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c irq->hw_idx = phys_enc->hw_ctl->idx; phys_enc 163 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c irq = &phys_enc->irq[INTR_IDX_PINGPONG]; phys_enc 164 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c irq->hw_idx = phys_enc->hw_pp->idx; phys_enc 167 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c irq = &phys_enc->irq[INTR_IDX_RDPTR]; phys_enc 168 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c irq->hw_idx = phys_enc->hw_pp->idx; phys_enc 171 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c irq = &phys_enc->irq[INTR_IDX_UNDERRUN]; phys_enc 172 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c irq->hw_idx = phys_enc->intf_idx; phys_enc 177 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c struct dpu_encoder_phys *phys_enc, phys_enc 182 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c to_dpu_encoder_phys_cmd(phys_enc); phys_enc 184 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c if (!phys_enc || !mode || !adj_mode) { phys_enc 188 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c phys_enc->cached_mode = *adj_mode; phys_enc 192 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c _dpu_encoder_phys_cmd_setup_irq_hw_idx(phys_enc); phys_enc 196 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c struct dpu_encoder_phys *phys_enc) phys_enc 199 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c to_dpu_encoder_phys_cmd(phys_enc); phys_enc 203 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c if (!phys_enc || !phys_enc->hw_pp || !phys_enc->hw_ctl) phys_enc 214 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c trace_dpu_enc_phys_cmd_pdone_timeout(DRMID(phys_enc->parent), phys_enc 215 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c phys_enc->hw_pp->idx - PINGPONG_0, phys_enc 217 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c atomic_read(&phys_enc->pending_kickoff_cnt), phys_enc 223 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c DRMID(phys_enc->parent), phys_enc 224 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c phys_enc->hw_pp->idx - PINGPONG_0, phys_enc 225 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c phys_enc->hw_ctl->idx - CTL_0, phys_enc 227 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c atomic_read(&phys_enc->pending_kickoff_cnt)); phys_enc 229 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c dpu_encoder_helper_unregister_irq(phys_enc, INTR_IDX_RDPTR); phys_enc 232 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c atomic_add_unless(&phys_enc->pending_kickoff_cnt, -1, 0); phys_enc 235 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c phys_enc->enable_state = DPU_ENC_ERR_NEEDS_HW_RESET; phys_enc 237 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c if (phys_enc->parent_ops->handle_frame_done) phys_enc 238 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c phys_enc->parent_ops->handle_frame_done( phys_enc 239 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c phys_enc->parent, phys_enc, frame_event); phys_enc 245 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c struct dpu_encoder_phys *phys_enc) phys_enc 248 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c to_dpu_encoder_phys_cmd(phys_enc); phys_enc 252 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c if (!phys_enc) { phys_enc 257 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c wait_info.wq = &phys_enc->pending_kickoff_wq; phys_enc 258 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c wait_info.atomic_cnt = &phys_enc->pending_kickoff_cnt; phys_enc 261 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c ret = dpu_encoder_helper_wait_for_irq(phys_enc, INTR_IDX_PINGPONG, phys_enc 264 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c _dpu_encoder_phys_cmd_handle_ppdone_timeout(phys_enc); phys_enc 272 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c struct dpu_encoder_phys *phys_enc, phys_enc 278 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c if (!phys_enc || !phys_enc->hw_pp) { phys_enc 283 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c refcount = atomic_read(&phys_enc->vblank_refcount); phys_enc 286 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c if (!dpu_encoder_phys_cmd_is_master(phys_enc)) phys_enc 295 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c DRM_DEBUG_KMS("id:%u pp:%d enable=%s/%d\n", DRMID(phys_enc->parent), phys_enc 296 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c phys_enc->hw_pp->idx - PINGPONG_0, phys_enc 299 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c if (enable && atomic_inc_return(&phys_enc->vblank_refcount) == 1) phys_enc 300 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c ret = dpu_encoder_helper_register_irq(phys_enc, INTR_IDX_RDPTR); phys_enc 301 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c else if (!enable && atomic_dec_return(&phys_enc->vblank_refcount) == 0) phys_enc 302 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c ret = dpu_encoder_helper_unregister_irq(phys_enc, phys_enc 308 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c DRMID(phys_enc->parent), phys_enc 309 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c phys_enc->hw_pp->idx - PINGPONG_0, ret, phys_enc 316 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c static void dpu_encoder_phys_cmd_irq_control(struct dpu_encoder_phys *phys_enc, phys_enc 321 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c if (!phys_enc) phys_enc 324 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c cmd_enc = to_dpu_encoder_phys_cmd(phys_enc); phys_enc 326 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c trace_dpu_enc_phys_cmd_irq_ctrl(DRMID(phys_enc->parent), phys_enc 327 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c phys_enc->hw_pp->idx - PINGPONG_0, phys_enc 328 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c enable, atomic_read(&phys_enc->vblank_refcount)); phys_enc 331 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c dpu_encoder_helper_register_irq(phys_enc, INTR_IDX_PINGPONG); phys_enc 332 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c dpu_encoder_helper_register_irq(phys_enc, INTR_IDX_UNDERRUN); phys_enc 333 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c dpu_encoder_phys_cmd_control_vblank_irq(phys_enc, true); phys_enc 335 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c if (dpu_encoder_phys_cmd_is_master(phys_enc)) phys_enc 336 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c dpu_encoder_helper_register_irq(phys_enc, phys_enc 339 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c if (dpu_encoder_phys_cmd_is_master(phys_enc)) phys_enc 340 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c dpu_encoder_helper_unregister_irq(phys_enc, phys_enc 343 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c dpu_encoder_helper_unregister_irq(phys_enc, INTR_IDX_UNDERRUN); phys_enc 344 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c dpu_encoder_phys_cmd_control_vblank_irq(phys_enc, false); phys_enc 345 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c dpu_encoder_helper_unregister_irq(phys_enc, INTR_IDX_PINGPONG); phys_enc 350 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c struct dpu_encoder_phys *phys_enc) phys_enc 353 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c to_dpu_encoder_phys_cmd(phys_enc); phys_enc 361 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c if (!phys_enc || !phys_enc->hw_pp) { phys_enc 365 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c mode = &phys_enc->cached_mode; phys_enc 367 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c DPU_DEBUG_CMDENC(cmd_enc, "pp %d\n", phys_enc->hw_pp->idx - PINGPONG_0); phys_enc 369 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c if (!phys_enc->hw_pp->ops.setup_tearcheck || phys_enc 370 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c !phys_enc->hw_pp->ops.enable_tearcheck) { phys_enc 375 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c dpu_kms = phys_enc->dpu_kms; phys_enc 418 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c phys_enc->hw_pp->idx - PINGPONG_0, vsync_hz, phys_enc 422 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c phys_enc->hw_pp->idx - PINGPONG_0, tc_enable, tc_cfg.start_pos, phys_enc 426 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c phys_enc->hw_pp->idx - PINGPONG_0, tc_cfg.hw_vsync_mode, phys_enc 430 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c phys_enc->hw_pp->idx - PINGPONG_0, tc_cfg.sync_cfg_height, phys_enc 433 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c phys_enc->hw_pp->ops.setup_tearcheck(phys_enc->hw_pp, &tc_cfg); phys_enc 434 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c phys_enc->hw_pp->ops.enable_tearcheck(phys_enc->hw_pp, tc_enable); phys_enc 438 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c struct dpu_encoder_phys *phys_enc) phys_enc 441 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c to_dpu_encoder_phys_cmd(phys_enc); phys_enc 443 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c if (!phys_enc || !phys_enc->hw_ctl || !phys_enc->hw_pp phys_enc 444 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c || !phys_enc->hw_ctl->ops.setup_intf_cfg) { phys_enc 445 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c DPU_ERROR("invalid arg(s), enc %d\n", phys_enc != 0); phys_enc 450 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c phys_enc->hw_pp->idx - PINGPONG_0); phys_enc 451 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c drm_mode_debug_printmodeline(&phys_enc->cached_mode); phys_enc 453 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c _dpu_encoder_phys_cmd_update_intf_cfg(phys_enc); phys_enc 454 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c dpu_encoder_phys_cmd_tearcheck_config(phys_enc); phys_enc 458 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c struct dpu_encoder_phys *phys_enc) phys_enc 468 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c struct dpu_encoder_phys *phys_enc) phys_enc 473 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c if (!phys_enc || !phys_enc->hw_ctl || !phys_enc->hw_pp) { phys_enc 474 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c DPU_ERROR("invalid arg(s), encoder %d\n", phys_enc != 0); phys_enc 478 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c dpu_encoder_helper_split_config(phys_enc, phys_enc->intf_idx); phys_enc 480 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c _dpu_encoder_phys_cmd_pingpong_config(phys_enc); phys_enc 482 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c if (!dpu_encoder_phys_cmd_is_master(phys_enc)) phys_enc 485 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c ctl = phys_enc->hw_ctl; phys_enc 486 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c ctl->ops.get_bitmask_intf(ctl, &flush_mask, phys_enc->intf_idx); phys_enc 490 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c static void dpu_encoder_phys_cmd_enable(struct dpu_encoder_phys *phys_enc) phys_enc 493 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c to_dpu_encoder_phys_cmd(phys_enc); phys_enc 495 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c if (!phys_enc || !phys_enc->hw_pp) { phys_enc 500 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c DPU_DEBUG_CMDENC(cmd_enc, "pp %d\n", phys_enc->hw_pp->idx - PINGPONG_0); phys_enc 502 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c if (phys_enc->enable_state == DPU_ENC_ENABLED) { phys_enc 507 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c dpu_encoder_phys_cmd_enable_helper(phys_enc); phys_enc 508 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c phys_enc->enable_state = DPU_ENC_ENABLED; phys_enc 512 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c struct dpu_encoder_phys *phys_enc, bool enable) phys_enc 514 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c if (!phys_enc || !phys_enc->hw_pp || phys_enc 515 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c !phys_enc->hw_pp->ops.connect_external_te) phys_enc 518 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c trace_dpu_enc_phys_cmd_connect_te(DRMID(phys_enc->parent), enable); phys_enc 519 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c phys_enc->hw_pp->ops.connect_external_te(phys_enc->hw_pp, enable); phys_enc 523 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c struct dpu_encoder_phys *phys_enc) phys_enc 525 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c _dpu_encoder_phys_cmd_connect_te(phys_enc, false); phys_enc 529 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c struct dpu_encoder_phys *phys_enc) phys_enc 533 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c if (!phys_enc || !phys_enc->hw_pp) phys_enc 536 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c if (!dpu_encoder_phys_cmd_is_master(phys_enc)) phys_enc 539 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c hw_pp = phys_enc->hw_pp; phys_enc 546 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c static void dpu_encoder_phys_cmd_disable(struct dpu_encoder_phys *phys_enc) phys_enc 549 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c to_dpu_encoder_phys_cmd(phys_enc); phys_enc 551 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c if (!phys_enc || !phys_enc->hw_pp) { phys_enc 555 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c DRM_DEBUG_KMS("id:%u pp:%d state:%d\n", DRMID(phys_enc->parent), phys_enc 556 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c phys_enc->hw_pp->idx - PINGPONG_0, phys_enc 557 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c phys_enc->enable_state); phys_enc 559 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c if (phys_enc->enable_state == DPU_ENC_DISABLED) { phys_enc 564 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c if (phys_enc->hw_pp->ops.enable_tearcheck) phys_enc 565 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c phys_enc->hw_pp->ops.enable_tearcheck(phys_enc->hw_pp, false); phys_enc 566 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c phys_enc->enable_state = DPU_ENC_DISABLED; phys_enc 569 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c static void dpu_encoder_phys_cmd_destroy(struct dpu_encoder_phys *phys_enc) phys_enc 572 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c to_dpu_encoder_phys_cmd(phys_enc); phys_enc 574 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c if (!phys_enc) { phys_enc 582 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c struct dpu_encoder_phys *phys_enc, phys_enc 585 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c hw_res->intfs[phys_enc->intf_idx - INTF_0] = INTF_MODE_CMD; phys_enc 589 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c struct dpu_encoder_phys *phys_enc) phys_enc 592 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c to_dpu_encoder_phys_cmd(phys_enc); phys_enc 595 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c if (!phys_enc || !phys_enc->hw_pp) { phys_enc 599 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c DRM_DEBUG_KMS("id:%u pp:%d pending_cnt:%d\n", DRMID(phys_enc->parent), phys_enc 600 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c phys_enc->hw_pp->idx - PINGPONG_0, phys_enc 601 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c atomic_read(&phys_enc->pending_kickoff_cnt)); phys_enc 607 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c ret = _dpu_encoder_phys_cmd_wait_for_idle(phys_enc); phys_enc 610 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c atomic_set(&phys_enc->pending_kickoff_cnt, 0); phys_enc 612 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c DRMID(phys_enc->parent), ret, phys_enc 613 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c phys_enc->hw_pp->idx - PINGPONG_0); phys_enc 617 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c phys_enc->hw_pp->idx - PINGPONG_0, phys_enc 618 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c atomic_read(&phys_enc->pending_kickoff_cnt)); phys_enc 622 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c struct dpu_encoder_phys *phys_enc) phys_enc 625 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c to_dpu_encoder_phys_cmd(phys_enc); phys_enc 629 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c if (!phys_enc || !phys_enc->hw_ctl) { phys_enc 634 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c wait_info.wq = &phys_enc->pending_kickoff_wq; phys_enc 635 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c wait_info.atomic_cnt = &phys_enc->pending_ctlstart_cnt; phys_enc 638 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c ret = dpu_encoder_helper_wait_for_irq(phys_enc, INTR_IDX_CTL_START, phys_enc 650 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c struct dpu_encoder_phys *phys_enc) phys_enc 655 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c if (!phys_enc) phys_enc 658 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c cmd_enc = to_dpu_encoder_phys_cmd(phys_enc); phys_enc 660 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c rc = _dpu_encoder_phys_cmd_wait_for_idle(phys_enc); phys_enc 663 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c DRMID(phys_enc->parent), rc, phys_enc 664 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c phys_enc->intf_idx - INTF_0); phys_enc 671 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c struct dpu_encoder_phys *phys_enc) phys_enc 676 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c if (!phys_enc) phys_enc 679 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c cmd_enc = to_dpu_encoder_phys_cmd(phys_enc); phys_enc 682 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c if (dpu_encoder_phys_cmd_is_master(phys_enc)) phys_enc 683 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c rc = _dpu_encoder_phys_cmd_wait_for_ctl_start(phys_enc); phys_enc 687 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c dpu_encoder_phys_cmd_prepare_for_kickoff(phys_enc); phys_enc 693 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c struct dpu_encoder_phys *phys_enc) phys_enc 699 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c if (!phys_enc) phys_enc 702 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c cmd_enc = to_dpu_encoder_phys_cmd(phys_enc); phys_enc 705 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c if (!dpu_encoder_phys_cmd_is_master(phys_enc)) phys_enc 714 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c rc = dpu_encoder_helper_wait_for_irq(phys_enc, INTR_IDX_RDPTR, phys_enc 721 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c struct dpu_encoder_phys *phys_enc) phys_enc 727 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c _dpu_encoder_phys_cmd_connect_te(phys_enc, true); phys_enc 731 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c struct dpu_encoder_phys *phys_enc) phys_enc 733 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c if (!phys_enc) phys_enc 736 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c dpu_encoder_helper_trigger_start(phys_enc); phys_enc 766 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c struct dpu_encoder_phys *phys_enc = NULL; phys_enc 779 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c phys_enc = &cmd_enc->base; phys_enc 780 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c phys_enc->hw_mdptop = p->dpu_kms->hw_mdp; phys_enc 781 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c phys_enc->intf_idx = p->intf_idx; phys_enc 783 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c dpu_encoder_phys_cmd_init_ops(&phys_enc->ops); phys_enc 784 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c phys_enc->parent = p->parent; phys_enc 785 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c phys_enc->parent_ops = p->parent_ops; phys_enc 786 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c phys_enc->dpu_kms = p->dpu_kms; phys_enc 787 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c phys_enc->split_role = p->split_role; phys_enc 788 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c phys_enc->intf_mode = INTF_MODE_CMD; phys_enc 789 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c phys_enc->enc_spinlock = p->enc_spinlock; phys_enc 791 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c phys_enc->enable_state = DPU_ENC_DISABLED; phys_enc 793 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c irq = &phys_enc->irq[i]; phys_enc 797 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c irq->cb.arg = phys_enc; phys_enc 800 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c irq = &phys_enc->irq[INTR_IDX_CTL_START]; phys_enc 806 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c irq = &phys_enc->irq[INTR_IDX_PINGPONG]; phys_enc 812 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c irq = &phys_enc->irq[INTR_IDX_RDPTR]; phys_enc 818 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c irq = &phys_enc->irq[INTR_IDX_UNDERRUN]; phys_enc 824 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c atomic_set(&phys_enc->vblank_refcount, 0); phys_enc 825 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c atomic_set(&phys_enc->pending_kickoff_cnt, 0); phys_enc 826 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c atomic_set(&phys_enc->pending_ctlstart_cnt, 0); phys_enc 828 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c init_waitqueue_head(&phys_enc->pending_kickoff_wq); phys_enc 833 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c return phys_enc; phys_enc 28 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c struct dpu_encoder_phys *phys_enc) phys_enc 32 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c if (phys_enc->split_role != ENC_ROLE_SLAVE) phys_enc 39 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c const struct dpu_encoder_phys *phys_enc, phys_enc 87 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c if (phys_enc->hw_intf->cap->type == INTF_DSI) { phys_enc 138 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c struct dpu_encoder_phys *phys_enc, phys_enc 142 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c phys_enc->hw_intf->cap->prog_fetch_lines_worst_case; phys_enc 150 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c DPU_DEBUG_VIDENC(phys_enc, phys_enc 157 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c DPU_DEBUG_VIDENC(phys_enc, phys_enc 161 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c DPU_DEBUG_VIDENC(phys_enc, "room in vfp for needed prefetch\n"); phys_enc 165 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c DPU_DEBUG_VIDENC(phys_enc, phys_enc 169 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c DPU_DEBUG_VIDENC(phys_enc, phys_enc 186 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c static void programmable_fetch_config(struct dpu_encoder_phys *phys_enc, phys_enc 196 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c if (WARN_ON_ONCE(!phys_enc->hw_intf->ops.setup_prg_fetch)) phys_enc 199 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c vfp_fetch_lines = programmable_fetch_get_num_lines(phys_enc, timing); phys_enc 209 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c DPU_DEBUG_VIDENC(phys_enc, phys_enc 213 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags); phys_enc 214 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c phys_enc->hw_intf->ops.setup_prg_fetch(phys_enc->hw_intf, &f); phys_enc 215 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags); phys_enc 219 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c struct dpu_encoder_phys *phys_enc, phys_enc 223 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c if (phys_enc) phys_enc 224 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c DPU_DEBUG_VIDENC(phys_enc, "\n"); phys_enc 233 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c struct dpu_encoder_phys *phys_enc) phys_enc 242 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c if (!phys_enc || !phys_enc->hw_ctl->ops.setup_intf_cfg) { phys_enc 243 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c DPU_ERROR("invalid encoder %d\n", phys_enc != 0); phys_enc 247 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c mode = phys_enc->cached_mode; phys_enc 248 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c if (!phys_enc->hw_intf->ops.setup_timing_gen) { phys_enc 253 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c DPU_DEBUG_VIDENC(phys_enc, "enabling mode:\n"); phys_enc 256 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c if (phys_enc->split_role != ENC_ROLE_SOLO) { phys_enc 262 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c DPU_DEBUG_VIDENC(phys_enc, phys_enc 264 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c phys_enc->split_role, phys_enc 269 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c drm_mode_to_intf_timing_params(phys_enc, &mode, &timing_params); phys_enc 272 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c DPU_DEBUG_VIDENC(phys_enc, "fmt_fourcc 0x%X\n", fmt_fourcc); phys_enc 274 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c intf_cfg.intf = phys_enc->hw_intf->idx; phys_enc 277 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc); phys_enc 279 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags); phys_enc 280 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c phys_enc->hw_intf->ops.setup_timing_gen(phys_enc->hw_intf, phys_enc 282 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg); phys_enc 283 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags); phys_enc 285 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c programmable_fetch_config(phys_enc, &timing_params); phys_enc 290 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c struct dpu_encoder_phys *phys_enc = arg; phys_enc 296 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c if (!phys_enc) phys_enc 299 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c hw_ctl = phys_enc->hw_ctl; phys_enc 305 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c if (phys_enc->parent_ops->handle_vblank_virt) phys_enc 306 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c phys_enc->parent_ops->handle_vblank_virt(phys_enc->parent, phys_enc 307 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c phys_enc); phys_enc 309 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c old_cnt = atomic_read(&phys_enc->pending_kickoff_cnt); phys_enc 316 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags); phys_enc 321 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c new_cnt = atomic_add_unless(&phys_enc->pending_kickoff_cnt, phys_enc 323 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags); phys_enc 326 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c wake_up_all(&phys_enc->pending_kickoff_wq); phys_enc 328 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c phys_enc->parent_ops->handle_frame_done(phys_enc->parent, phys_enc, phys_enc 336 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c struct dpu_encoder_phys *phys_enc = arg; phys_enc 338 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c if (!phys_enc) phys_enc 341 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c if (phys_enc->parent_ops->handle_underrun_virt) phys_enc 342 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c phys_enc->parent_ops->handle_underrun_virt(phys_enc->parent, phys_enc 343 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c phys_enc); phys_enc 347 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c struct dpu_encoder_phys *phys_enc) phys_enc 349 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c return phys_enc->split_role != ENC_ROLE_SOLO; phys_enc 353 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c struct dpu_encoder_phys *phys_enc) phys_enc 363 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c irq = &phys_enc->irq[INTR_IDX_VSYNC]; phys_enc 365 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c irq->hw_idx = phys_enc->intf_idx; phys_enc 367 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c irq = &phys_enc->irq[INTR_IDX_UNDERRUN]; phys_enc 369 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c irq->hw_idx = phys_enc->intf_idx; phys_enc 373 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c struct dpu_encoder_phys *phys_enc, phys_enc 377 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c if (!phys_enc || !phys_enc->dpu_kms) { phys_enc 383 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c phys_enc->cached_mode = *adj_mode; phys_enc 385 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c DPU_DEBUG_VIDENC(phys_enc, "caching mode:\n"); phys_enc 388 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c _dpu_encoder_phys_vid_setup_irq_hw_idx(phys_enc); phys_enc 392 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c struct dpu_encoder_phys *phys_enc, phys_enc 398 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c if (!phys_enc) { phys_enc 403 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c refcount = atomic_read(&phys_enc->vblank_refcount); phys_enc 406 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c if (!dpu_encoder_phys_vid_is_master(phys_enc)) phys_enc 415 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c DRM_DEBUG_KMS("id:%u enable=%d/%d\n", DRMID(phys_enc->parent), enable, phys_enc 416 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c atomic_read(&phys_enc->vblank_refcount)); phys_enc 418 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c if (enable && atomic_inc_return(&phys_enc->vblank_refcount) == 1) phys_enc 419 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c ret = dpu_encoder_helper_register_irq(phys_enc, INTR_IDX_VSYNC); phys_enc 420 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c else if (!enable && atomic_dec_return(&phys_enc->vblank_refcount) == 0) phys_enc 421 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c ret = dpu_encoder_helper_unregister_irq(phys_enc, phys_enc 427 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c DRMID(phys_enc->parent), phys_enc 428 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c phys_enc->hw_intf->idx - INTF_0, ret, enable, phys_enc 434 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c static void dpu_encoder_phys_vid_enable(struct dpu_encoder_phys *phys_enc) phys_enc 439 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c ctl = phys_enc->hw_ctl; phys_enc 441 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c DPU_DEBUG_VIDENC(phys_enc, "\n"); phys_enc 443 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c if (WARN_ON(!phys_enc->hw_intf->ops.enable_timing)) phys_enc 446 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c dpu_encoder_helper_split_config(phys_enc, phys_enc->hw_intf->idx); phys_enc 448 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c dpu_encoder_phys_vid_setup_timing_engine(phys_enc); phys_enc 455 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c if (dpu_encoder_phys_vid_needs_single_flush(phys_enc) && phys_enc 456 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c !dpu_encoder_phys_vid_is_master(phys_enc)) phys_enc 459 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c ctl->ops.get_bitmask_intf(ctl, &flush_mask, phys_enc->hw_intf->idx); phys_enc 463 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c DPU_DEBUG_VIDENC(phys_enc, phys_enc 468 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c if (phys_enc->enable_state == DPU_ENC_DISABLED) phys_enc 469 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c phys_enc->enable_state = DPU_ENC_ENABLING; phys_enc 472 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c static void dpu_encoder_phys_vid_destroy(struct dpu_encoder_phys *phys_enc) phys_enc 474 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c if (!phys_enc) { phys_enc 479 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c DPU_DEBUG_VIDENC(phys_enc, "\n"); phys_enc 480 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c kfree(phys_enc); phys_enc 484 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c struct dpu_encoder_phys *phys_enc, phys_enc 487 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c hw_res->intfs[phys_enc->intf_idx - INTF_0] = INTF_MODE_VIDEO; phys_enc 491 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c struct dpu_encoder_phys *phys_enc) phys_enc 496 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c if (!phys_enc) { phys_enc 501 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c wait_info.wq = &phys_enc->pending_kickoff_wq; phys_enc 502 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c wait_info.atomic_cnt = &phys_enc->pending_kickoff_cnt; phys_enc 505 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c if (!dpu_encoder_phys_vid_is_master(phys_enc)) { phys_enc 510 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c ret = dpu_encoder_helper_wait_for_irq(phys_enc, INTR_IDX_VSYNC, phys_enc 514 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c dpu_encoder_helper_report_irq_timeout(phys_enc, INTR_IDX_VSYNC); phys_enc 521 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c struct dpu_encoder_phys *phys_enc) phys_enc 523 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c struct dpu_hw_ctl *hw_ctl = phys_enc->hw_ctl; phys_enc 529 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c ret = wait_event_timeout(phys_enc->pending_kickoff_wq, phys_enc 541 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c struct dpu_encoder_phys *phys_enc) phys_enc 546 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c if (!phys_enc) { phys_enc 551 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c ctl = phys_enc->hw_ctl; phys_enc 561 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c DPU_ERROR_VIDENC(phys_enc, "ctl %d reset failure: %d\n", phys_enc 563 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c dpu_encoder_helper_unregister_irq(phys_enc, INTR_IDX_VSYNC); phys_enc 567 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c static void dpu_encoder_phys_vid_disable(struct dpu_encoder_phys *phys_enc) phys_enc 573 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c if (!phys_enc || !phys_enc->parent || !phys_enc->parent->dev || phys_enc 574 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c !phys_enc->parent->dev->dev_private) { phys_enc 578 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c priv = phys_enc->parent->dev->dev_private; phys_enc 580 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c if (!phys_enc->hw_intf || !phys_enc->hw_ctl) { phys_enc 582 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c phys_enc->hw_intf != 0, phys_enc->hw_ctl != 0); phys_enc 586 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c if (WARN_ON(!phys_enc->hw_intf->ops.enable_timing)) phys_enc 589 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c if (phys_enc->enable_state == DPU_ENC_DISABLED) { phys_enc 594 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags); phys_enc 595 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c phys_enc->hw_intf->ops.enable_timing(phys_enc->hw_intf, 0); phys_enc 596 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c if (dpu_encoder_phys_vid_is_master(phys_enc)) phys_enc 597 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c dpu_encoder_phys_inc_pending(phys_enc); phys_enc 598 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags); phys_enc 608 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c if (dpu_encoder_phys_vid_is_master(phys_enc)) { phys_enc 609 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c ret = dpu_encoder_phys_vid_wait_for_vblank(phys_enc); phys_enc 611 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c atomic_set(&phys_enc->pending_kickoff_cnt, 0); phys_enc 613 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c DRMID(phys_enc->parent), phys_enc 614 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c phys_enc->hw_intf->idx - INTF_0, ret); phys_enc 618 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c phys_enc->enable_state = DPU_ENC_DISABLED; phys_enc 622 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c struct dpu_encoder_phys *phys_enc) phys_enc 630 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c if (phys_enc->enable_state == DPU_ENC_ENABLING) { phys_enc 631 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c trace_dpu_enc_phys_vid_post_kickoff(DRMID(phys_enc->parent), phys_enc 632 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c phys_enc->hw_intf->idx - INTF_0); phys_enc 633 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags); phys_enc 634 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c phys_enc->hw_intf->ops.enable_timing(phys_enc->hw_intf, 1); phys_enc 635 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags); phys_enc 636 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c phys_enc->enable_state = DPU_ENC_ENABLED; phys_enc 640 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c static void dpu_encoder_phys_vid_irq_control(struct dpu_encoder_phys *phys_enc, phys_enc 645 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c if (!phys_enc) phys_enc 648 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c trace_dpu_enc_phys_vid_irq_ctrl(DRMID(phys_enc->parent), phys_enc 649 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c phys_enc->hw_intf->idx - INTF_0, phys_enc 651 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c atomic_read(&phys_enc->vblank_refcount)); phys_enc 654 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c ret = dpu_encoder_phys_vid_control_vblank_irq(phys_enc, true); phys_enc 658 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c dpu_encoder_helper_register_irq(phys_enc, INTR_IDX_UNDERRUN); phys_enc 660 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c dpu_encoder_phys_vid_control_vblank_irq(phys_enc, false); phys_enc 661 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c dpu_encoder_helper_unregister_irq(phys_enc, INTR_IDX_UNDERRUN); phys_enc 666 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c struct dpu_encoder_phys *phys_enc) phys_enc 668 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c if (!phys_enc) phys_enc 671 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c if (!dpu_encoder_phys_vid_is_master(phys_enc)) phys_enc 674 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c if (!phys_enc->hw_intf || !phys_enc->hw_intf->ops.get_line_count) phys_enc 677 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c return phys_enc->hw_intf->ops.get_line_count(phys_enc->hw_intf); phys_enc 703 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c struct dpu_encoder_phys *phys_enc = NULL; phys_enc 712 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c phys_enc = kzalloc(sizeof(*phys_enc), GFP_KERNEL); phys_enc 713 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c if (!phys_enc) { phys_enc 718 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c phys_enc->hw_mdptop = p->dpu_kms->hw_mdp; phys_enc 719 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c phys_enc->intf_idx = p->intf_idx; phys_enc 721 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c DPU_DEBUG_VIDENC(phys_enc, "\n"); phys_enc 723 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c dpu_encoder_phys_vid_init_ops(&phys_enc->ops); phys_enc 724 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c phys_enc->parent = p->parent; phys_enc 725 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c phys_enc->parent_ops = p->parent_ops; phys_enc 726 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c phys_enc->dpu_kms = p->dpu_kms; phys_enc 727 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c phys_enc->split_role = p->split_role; phys_enc 728 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c phys_enc->intf_mode = INTF_MODE_VIDEO; phys_enc 729 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c phys_enc->enc_spinlock = p->enc_spinlock; phys_enc 731 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c irq = &phys_enc->irq[i]; phys_enc 735 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c irq->cb.arg = phys_enc; phys_enc 738 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c irq = &phys_enc->irq[INTR_IDX_VSYNC]; phys_enc 744 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c irq = &phys_enc->irq[INTR_IDX_UNDERRUN]; phys_enc 750 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c atomic_set(&phys_enc->vblank_refcount, 0); phys_enc 751 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c atomic_set(&phys_enc->pending_kickoff_cnt, 0); phys_enc 752 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c init_waitqueue_head(&phys_enc->pending_kickoff_wq); phys_enc 753 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c phys_enc->enable_state = DPU_ENC_DISABLED; phys_enc 755 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c DPU_DEBUG_VIDENC(phys_enc, "created intf idx:%d\n", p->intf_idx); phys_enc 757 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c return phys_enc; phys_enc 761 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c if (phys_enc) phys_enc 762 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c dpu_encoder_phys_vid_destroy(phys_enc);