phyreg 970 drivers/net/ethernet/dec/tulip/de4x5.c static int mii_rd(u_char phyreg, u_char phyaddr, u_long ioaddr); phyreg 971 drivers/net/ethernet/dec/tulip/de4x5.c static void mii_wr(int data, u_char phyreg, u_char phyaddr, u_long ioaddr); phyreg 4808 drivers/net/ethernet/dec/tulip/de4x5.c mii_rd(u_char phyreg, u_char phyaddr, u_long ioaddr) phyreg 4814 drivers/net/ethernet/dec/tulip/de4x5.c mii_address(phyreg, ioaddr); /* PHY Register to read */ phyreg 4821 drivers/net/ethernet/dec/tulip/de4x5.c mii_wr(int data, u_char phyreg, u_char phyaddr, u_long ioaddr) phyreg 4827 drivers/net/ethernet/dec/tulip/de4x5.c mii_address(phyreg, ioaddr); /* PHY Register to write */ phyreg 3273 drivers/net/ethernet/nvidia/forcedeth.c u32 phyreg, txreg; phyreg 3283 drivers/net/ethernet/nvidia/forcedeth.c phyreg = readl(base + NvRegSlotTime); phyreg 3284 drivers/net/ethernet/nvidia/forcedeth.c phyreg &= ~(0x3FF00); phyreg 3286 drivers/net/ethernet/nvidia/forcedeth.c phyreg |= NVREG_SLOTTIME_10_100_FULL; phyreg 3288 drivers/net/ethernet/nvidia/forcedeth.c phyreg |= NVREG_SLOTTIME_10_100_FULL; phyreg 3290 drivers/net/ethernet/nvidia/forcedeth.c phyreg |= NVREG_SLOTTIME_1000_FULL; phyreg 3291 drivers/net/ethernet/nvidia/forcedeth.c writel(phyreg, base + NvRegSlotTime); phyreg 3294 drivers/net/ethernet/nvidia/forcedeth.c phyreg = readl(base + NvRegPhyInterface); phyreg 3295 drivers/net/ethernet/nvidia/forcedeth.c phyreg &= ~(PHY_HALF|PHY_100|PHY_1000); phyreg 3297 drivers/net/ethernet/nvidia/forcedeth.c phyreg |= PHY_HALF; phyreg 3299 drivers/net/ethernet/nvidia/forcedeth.c phyreg |= PHY_100; phyreg 3302 drivers/net/ethernet/nvidia/forcedeth.c phyreg |= PHY_1000; phyreg 3303 drivers/net/ethernet/nvidia/forcedeth.c writel(phyreg, base + NvRegPhyInterface); phyreg 3305 drivers/net/ethernet/nvidia/forcedeth.c if (phyreg & PHY_RGMII) { phyreg 3357 drivers/net/ethernet/nvidia/forcedeth.c u32 control_1000, status_1000, phyreg, pause_flags, txreg; phyreg 3466 drivers/net/ethernet/nvidia/forcedeth.c phyreg = readl(base + NvRegSlotTime); phyreg 3467 drivers/net/ethernet/nvidia/forcedeth.c phyreg &= ~(0x3FF00); phyreg 3470 drivers/net/ethernet/nvidia/forcedeth.c phyreg |= NVREG_SLOTTIME_10_100_FULL; phyreg 3472 drivers/net/ethernet/nvidia/forcedeth.c phyreg |= NVREG_SLOTTIME_1000_FULL; phyreg 3473 drivers/net/ethernet/nvidia/forcedeth.c writel(phyreg, base + NvRegSlotTime); phyreg 3476 drivers/net/ethernet/nvidia/forcedeth.c phyreg = readl(base + NvRegPhyInterface); phyreg 3477 drivers/net/ethernet/nvidia/forcedeth.c phyreg &= ~(PHY_HALF|PHY_100|PHY_1000); phyreg 3479 drivers/net/ethernet/nvidia/forcedeth.c phyreg |= PHY_HALF; phyreg 3481 drivers/net/ethernet/nvidia/forcedeth.c phyreg |= PHY_100; phyreg 3483 drivers/net/ethernet/nvidia/forcedeth.c phyreg |= PHY_1000; phyreg 3484 drivers/net/ethernet/nvidia/forcedeth.c writel(phyreg, base + NvRegPhyInterface); phyreg 3487 drivers/net/ethernet/nvidia/forcedeth.c if (phyreg & PHY_RGMII) { phyreg 668 drivers/net/ethernet/nxp/lpc_eth.c static int lpc_mdio_read(struct mii_bus *bus, int phy_id, int phyreg) phyreg 674 drivers/net/ethernet/nxp/lpc_eth.c writel(((phy_id << 8) | phyreg), LPC_ENET_MADR(pldat->net_base)); phyreg 690 drivers/net/ethernet/nxp/lpc_eth.c static int lpc_mdio_write(struct mii_bus *bus, int phy_id, int phyreg, phyreg 696 drivers/net/ethernet/nxp/lpc_eth.c writel(((phy_id << 8) | phyreg), LPC_ENET_MADR(pldat->net_base)); phyreg 6858 drivers/net/ethernet/realtek/r8169_main.c static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg) phyreg 6865 drivers/net/ethernet/realtek/r8169_main.c return rtl_readphy(tp, phyreg); phyreg 6869 drivers/net/ethernet/realtek/r8169_main.c int phyreg, u16 val) phyreg 6876 drivers/net/ethernet/realtek/r8169_main.c rtl_writephy(tp, phyreg, val); phyreg 53 drivers/net/ethernet/samsung/sxgbe/sxgbe_mdio.c int phyreg, u16 phydata) phyreg 58 drivers/net/ethernet/samsung/sxgbe/sxgbe_mdio.c reg = ((phyreg >> 16) & 0x1f) << 21; phyreg 59 drivers/net/ethernet/samsung/sxgbe/sxgbe_mdio.c reg |= (phyaddr << 16) | (phyreg & 0xffff); phyreg 66 drivers/net/ethernet/samsung/sxgbe/sxgbe_mdio.c int phyreg, u16 phydata) phyreg 73 drivers/net/ethernet/samsung/sxgbe/sxgbe_mdio.c reg = (phyaddr << 16) | (phyreg & 0x1f); phyreg 80 drivers/net/ethernet/samsung/sxgbe/sxgbe_mdio.c int phyreg, u16 phydata) phyreg 89 drivers/net/ethernet/samsung/sxgbe/sxgbe_mdio.c if (phyreg & MII_ADDR_C45) { phyreg 90 drivers/net/ethernet/samsung/sxgbe/sxgbe_mdio.c sxgbe_mdio_c45(sp, cmd, phyaddr, phyreg, phydata); phyreg 96 drivers/net/ethernet/samsung/sxgbe/sxgbe_mdio.c sxgbe_mdio_c22(sp, cmd, phyaddr, phyreg, phydata); phyreg 109 drivers/net/ethernet/samsung/sxgbe/sxgbe_mdio.c static int sxgbe_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg) phyreg 115 drivers/net/ethernet/samsung/sxgbe/sxgbe_mdio.c rc = sxgbe_mdio_access(priv, SXGBE_SMA_READ_CMD, phyaddr, phyreg, 0); phyreg 130 drivers/net/ethernet/samsung/sxgbe/sxgbe_mdio.c static int sxgbe_mdio_write(struct mii_bus *bus, int phyaddr, int phyreg, phyreg 136 drivers/net/ethernet/samsung/sxgbe/sxgbe_mdio.c return sxgbe_mdio_access(priv, SXGBE_SMA_WRITE_CMD, phyaddr, phyreg, phyreg 120 drivers/net/ethernet/sgi/meth.c static unsigned long mdio_read(struct meth_private *priv, unsigned long phyreg) phyreg 124 drivers/net/ethernet/sgi/meth.c mace->eth.phy_regs = (priv->phy_addr << 5) | (phyreg & 0x1f); phyreg 626 drivers/net/ethernet/smsc/smc911x.c static int smc911x_phy_read(struct net_device *dev, int phyaddr, int phyreg) phyreg 631 drivers/net/ethernet/smsc/smc911x.c SMC_GET_MII(lp, phyreg, phyaddr, phydata); phyreg 634 drivers/net/ethernet/smsc/smc911x.c __func__, phyaddr, phyreg, phydata); phyreg 642 drivers/net/ethernet/smsc/smc911x.c static void smc911x_phy_write(struct net_device *dev, int phyaddr, int phyreg, phyreg 648 drivers/net/ethernet/smsc/smc911x.c __func__, phyaddr, phyreg, phydata); phyreg 650 drivers/net/ethernet/smsc/smc911x.c SMC_SET_MII(lp, phyreg, phyaddr, phydata); phyreg 807 drivers/net/ethernet/smsc/smc91x.c static int smc_phy_read(struct net_device *dev, int phyaddr, int phyreg) phyreg 819 drivers/net/ethernet/smsc/smc91x.c smc_mii_out(dev, 6 << 10 | phyaddr << 5 | phyreg, 14); phyreg 828 drivers/net/ethernet/smsc/smc91x.c __func__, phyaddr, phyreg, phydata); phyreg 837 drivers/net/ethernet/smsc/smc91x.c static void smc_phy_write(struct net_device *dev, int phyaddr, int phyreg, phyreg 849 drivers/net/ethernet/smsc/smc91x.c smc_mii_out(dev, 5 << 28 | phyaddr << 23 | phyreg << 18 | 2 << 16 | phydata, 32); phyreg 855 drivers/net/ethernet/smsc/smc91x.c __func__, phyaddr, phyreg, phydata); phyreg 46 drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c int phyreg, u32 *hw_addr) phyreg 65 drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c *hw_addr = (phyaddr << 16) | (phyreg & 0x1f); phyreg 69 drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c static int stmmac_xgmac2_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg) phyreg 78 drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c if (phyreg & MII_ADDR_C45) { phyreg 81 drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c ret = stmmac_xgmac2_c22_format(priv, phyaddr, phyreg, &addr); phyreg 109 drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c int phyreg, u16 phydata) phyreg 118 drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c if (phyreg & MII_ADDR_C45) { phyreg 121 drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c ret = stmmac_xgmac2_c22_format(priv, phyaddr, phyreg, &addr); phyreg 155 drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c static int stmmac_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg) phyreg 167 drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask; phyreg 172 drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c if (phyreg & MII_ADDR_C45) { phyreg 175 drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c value |= ((phyreg >> MII_DEVADDR_C45_SHIFT) << phyreg 179 drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c data |= (phyreg & MII_REGADDR_C45_MASK) << phyreg 209 drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c static int stmmac_mdio_write(struct mii_bus *bus, int phyaddr, int phyreg, phyreg 222 drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask; phyreg 228 drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c if (phyreg & MII_ADDR_C45) { phyreg 231 drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c value |= ((phyreg >> MII_DEVADDR_C45_SHIFT) << phyreg 235 drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c data |= (phyreg & MII_REGADDR_C45_MASK) << phyreg 258 drivers/net/ethernet/xircom/xirc2ps_cs.c static unsigned mii_rd(unsigned int ioaddr, u_char phyaddr, u_char phyreg); phyreg 259 drivers/net/ethernet/xircom/xirc2ps_cs.c static void mii_wr(unsigned int ioaddr, u_char phyaddr, u_char phyreg, phyreg 420 drivers/net/ethernet/xircom/xirc2ps_cs.c mii_rd(unsigned int ioaddr, u_char phyaddr, u_char phyreg) phyreg 430 drivers/net/ethernet/xircom/xirc2ps_cs.c mii_wbits(ioaddr, phyreg, 5); /* PHY register to read */ phyreg 442 drivers/net/ethernet/xircom/xirc2ps_cs.c mii_wr(unsigned int ioaddr, u_char phyaddr, u_char phyreg, unsigned data, phyreg 452 drivers/net/ethernet/xircom/xirc2ps_cs.c mii_wbits(ioaddr, phyreg, 5); /* PHY Register to write */ phyreg 58 drivers/staging/rtl8188eu/hal/phy.c struct bb_reg_def *phyreg = &adapt->HalData->PHYRegDef[rfpath]; phyreg 68 drivers/staging/rtl8188eu/hal/phy.c tmplong2 = phy_query_bb_reg(adapt, phyreg->rfHSSIPara2, phyreg 78 drivers/staging/rtl8188eu/hal/phy.c phy_set_bb_reg(adapt, phyreg->rfHSSIPara2, bMaskDWord, tmplong2); phyreg 89 drivers/staging/rtl8188eu/hal/phy.c ret = phy_query_bb_reg(adapt, phyreg->rfLSSIReadBackPi, phyreg 92 drivers/staging/rtl8188eu/hal/phy.c ret = phy_query_bb_reg(adapt, phyreg->rfLSSIReadBack, phyreg 102 drivers/staging/rtl8188eu/hal/phy.c struct bb_reg_def *phyreg = &adapt->HalData->PHYRegDef[rfpath]; phyreg 106 drivers/staging/rtl8188eu/hal/phy.c phy_set_bb_reg(adapt, phyreg->rf3wireOffset, bMaskDWord, data_and_addr);