phy_ctrl_1_shdw   875 drivers/memory/emif.c 	writel(regs->phy_ctrl_1_shdw, base + EMIF_DDR_PHY_CTRL_1_SHDW);
phy_ctrl_1_shdw  1662 drivers/memory/emif.c 		regs->phy_ctrl_1_shdw = get_ddr_phy_ctrl_1_attilaphy_4d(
phy_ctrl_1_shdw  1665 drivers/memory/emif.c 		regs->phy_ctrl_1_shdw = get_phy_ctrl_1_intelliphy_4d5(freq, cl);
phy_ctrl_1_shdw   586 drivers/memory/emif.h 	u32 phy_ctrl_1_shdw;