phy1 81 drivers/gpio/gpio-stp-xway.c u8 phy1; /* 3 bits can be driven by phy1 */ phy1 184 drivers/gpio/gpio-stp-xway.c chip->phy1 << XWAY_STP_PHY1_SHIFT, phy1 192 drivers/gpio/gpio-stp-xway.c chip->reserved = (chip->phy2 << 5) | (chip->phy1 << 2) | chip->dsl; phy1 247 drivers/gpio/gpio-stp-xway.c chip->phy1 = phy & XWAY_STP_PHY_MASK; phy1 328 drivers/media/platform/omap3isp/ispcsiphy.c struct isp_csiphy *phy1 = &isp->isp_csiphy1; phy1 338 drivers/media/platform/omap3isp/ispcsiphy.c phy1->isp = isp; phy1 339 drivers/media/platform/omap3isp/ispcsiphy.c mutex_init(&phy1->mutex); phy1 342 drivers/media/platform/omap3isp/ispcsiphy.c phy1->csi2 = &isp->isp_csi2c; phy1 343 drivers/media/platform/omap3isp/ispcsiphy.c phy1->num_data_lanes = ISP_CSIPHY1_NUM_DATA_LANES; phy1 344 drivers/media/platform/omap3isp/ispcsiphy.c phy1->cfg_regs = OMAP3_ISP_IOMEM_CSI2C_REGS1; phy1 345 drivers/media/platform/omap3isp/ispcsiphy.c phy1->phy_regs = OMAP3_ISP_IOMEM_CSIPHY1; phy1 6029 drivers/net/ethernet/broadcom/tg3.c u32 phy1, phy2; phy1 6033 drivers/net/ethernet/broadcom/tg3.c tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1); phy1 6041 drivers/net/ethernet/broadcom/tg3.c if ((phy1 & 0x10) && !(phy2 & 0x20)) { phy1 257 drivers/staging/media/omap4iss/iss_csiphy.c struct iss_csiphy *phy1 = &iss->csiphy1; phy1 260 drivers/staging/media/omap4iss/iss_csiphy.c phy1->iss = iss; phy1 261 drivers/staging/media/omap4iss/iss_csiphy.c phy1->csi2 = &iss->csi2a; phy1 262 drivers/staging/media/omap4iss/iss_csiphy.c phy1->max_data_lanes = ISS_CSIPHY1_NUM_DATA_LANES; phy1 263 drivers/staging/media/omap4iss/iss_csiphy.c phy1->used_data_lanes = 0; phy1 264 drivers/staging/media/omap4iss/iss_csiphy.c phy1->cfg_regs = OMAP4_ISS_MEM_CSI2_A_REGS1; phy1 265 drivers/staging/media/omap4iss/iss_csiphy.c phy1->phy_regs = OMAP4_ISS_MEM_CAMERARX_CORE1; phy1 266 drivers/staging/media/omap4iss/iss_csiphy.c mutex_init(&phy1->mutex);