phid1             148 arch/powerpc/platforms/85xx/ksi8560.c 	uint pvid, svid, phid1;
phid1             168 arch/powerpc/platforms/85xx/ksi8560.c 	phid1 = mfspr(SPRN_HID1);
phid1             169 arch/powerpc/platforms/85xx/ksi8560.c 	seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
phid1             138 arch/powerpc/platforms/85xx/mpc85xx_ads.c 	uint pvid, svid, phid1;
phid1             148 arch/powerpc/platforms/85xx/mpc85xx_ads.c 	phid1 = mfspr(SPRN_HID1);
phid1             149 arch/powerpc/platforms/85xx/mpc85xx_ads.c 	seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
phid1             358 arch/powerpc/platforms/85xx/mpc85xx_cds.c 	uint pvid, svid, phid1;
phid1             370 arch/powerpc/platforms/85xx/mpc85xx_cds.c 	phid1 = mfspr(SPRN_HID1);
phid1             371 arch/powerpc/platforms/85xx/mpc85xx_cds.c 	seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
phid1              46 arch/powerpc/platforms/85xx/ppa8548.c 	uint32_t svid, phid1;
phid1              54 arch/powerpc/platforms/85xx/ppa8548.c 	phid1 = mfspr(SPRN_HID1);
phid1              55 arch/powerpc/platforms/85xx/ppa8548.c 	seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
phid1              96 arch/powerpc/platforms/85xx/sbc8548.c 	uint pvid, svid, phid1;
phid1             107 arch/powerpc/platforms/85xx/sbc8548.c 	phid1 = mfspr(SPRN_HID1);
phid1             108 arch/powerpc/platforms/85xx/sbc8548.c 	seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
phid1              71 arch/powerpc/platforms/85xx/stx_gp3.c 	uint pvid, svid, phid1;
phid1              81 arch/powerpc/platforms/85xx/stx_gp3.c 	phid1 = mfspr(SPRN_HID1);
phid1              82 arch/powerpc/platforms/85xx/stx_gp3.c 	seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
phid1              70 arch/powerpc/platforms/85xx/tqm85xx.c 	uint pvid, svid, phid1;
phid1              80 arch/powerpc/platforms/85xx/tqm85xx.c 	phid1 = mfspr(SPRN_HID1);
phid1              81 arch/powerpc/platforms/85xx/tqm85xx.c 	seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));