phases             41 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr_ppt.h 	uint8_t  phases;
phases             68 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr_ppt.h 	uint8_t phases;
phases            696 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 		dep_table->entries[i].phases = allowed_dep_table->entries[i].phases;
phases            182 drivers/gpu/drm/i915/gem/i915_gem_pm.c 	struct list_head *phases[] = {
phases            210 drivers/gpu/drm/i915/gem/i915_gem_pm.c 	for (phase = phases; *phase; phase++) {
phases            154 drivers/gpu/drm/i915/gem/i915_gem_shrinker.c 	} phases[] = {
phases            211 drivers/gpu/drm/i915/gem/i915_gem_shrinker.c 	for (phase = phases; phase->list; phase++) {
phases           1022 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 	} *phase, phases[] = {
phases           1033 drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c 	for (i = 0, phase = phases; ret == 0 && i < ARRAY_SIZE(phases);
phases           1004 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 	} phases[] = {
phases           1020 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 	typeof(*phases) *p;
phases           1023 drivers/gpu/drm/i915/gt/selftest_hangcheck.c 	for (p = phases; p->name; p++) {
phases           2119 drivers/gpu/drm/i915/gt/selftest_lrc.c 	} phases[] = {
phases           2150 drivers/gpu/drm/i915/gt/selftest_lrc.c 		for (p = phases; p->name; p++) {
phases            111 drivers/gpu/drm/i915/gt/selftest_timeline.c 	} phases[] = {
phases            140 drivers/gpu/drm/i915/gt/selftest_timeline.c 	for (p = phases; p->name; p++) {
phases            501 drivers/gpu/drm/i915/i915_gem_gtt.c 	struct list_head *phases[] = {
phases            508 drivers/gpu/drm/i915/i915_gem_gtt.c 	for (phase = phases; *phase; phase++) {
phases            370 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c 			} phases[] = {
phases            386 drivers/gpu/drm/i915/selftests/i915_gem_gtt.c 			for (p = phases; p->name; p++) {
phases            703 drivers/gpu/drm/i915/selftests/i915_vma.c 	} phases[] = {
phases            720 drivers/gpu/drm/i915/selftests/i915_vma.c 	for (p = phases; p->name; p++) { /* exercise both create/lookup */
phases            336 drivers/nfc/pn544/pn544.c 	u8 phases = 0;
phases            367 drivers/nfc/pn544/pn544.c 		phases |= 1;		/* Type A */
phases            369 drivers/nfc/pn544/pn544.c 		phases |= (1 << 2);	/* Type F 212 */
phases            370 drivers/nfc/pn544/pn544.c 		phases |= (1 << 3);	/* Type F 424 */
phases            373 drivers/nfc/pn544/pn544.c 	phases |= (1 << 5);		/* NFC active */
phases            376 drivers/nfc/pn544/pn544.c 			      PN544_PL_RDPHASES, &phases, 1);
phases            316 drivers/scsi/NCR5380.c } phases[] = {
phases            343 drivers/scsi/NCR5380.c 		for (i = 0; (phases[i].value != PHASE_UNKNOWN) &&
phases            344 drivers/scsi/NCR5380.c 		     (phases[i].value != (status & PHASE_MASK)); ++i)
phases            346 drivers/scsi/NCR5380.c 		shost_printk(KERN_DEBUG, instance, "phase %s\n", phases[i].name);
phases            249 drivers/scsi/arm/fas216.c 	static const char *phases[] = {
phases            256 drivers/scsi/arm/fas216.c 	return phases[stat & STAT_BUSMASK];
phases            261 drivers/scsi/arm/fas216.c 	static const char *phases[] = {
phases            275 drivers/scsi/arm/fas216.c 	if (info->scsi.phase < ARRAY_SIZE(phases) &&
phases            276 drivers/scsi/arm/fas216.c 	    phases[info->scsi.phase])
phases            277 drivers/scsi/arm/fas216.c 		return phases[info->scsi.phase];
phases           1192 drivers/vfio/pci/vfio_pci_config.c 	int ret, evcc, phases, vc_arb;
phases           1205 drivers/vfio/pci/vfio_pci_config.c 		phases = 128;
phases           1207 drivers/vfio/pci/vfio_pci_config.c 		phases = 64;
phases           1209 drivers/vfio/pci/vfio_pci_config.c 		phases = 32;
phases           1211 drivers/vfio/pci/vfio_pci_config.c 		phases = 0;
phases           1213 drivers/vfio/pci/vfio_pci_config.c 	vc_arb = phases * 4;