phaseinc 4997 drivers/gpu/drm/i915/display/intel_display.c u32 divsel, phaseinc, auxdiv, phasedir = 0; phaseinc 5016 drivers/gpu/drm/i915/display/intel_display.c phaseinc = desired_divisor % iclk_pi_range; phaseinc 5037 drivers/gpu/drm/i915/display/intel_display.c phaseinc); phaseinc 5046 drivers/gpu/drm/i915/display/intel_display.c temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); phaseinc 5072 drivers/gpu/drm/i915/display/intel_display.c u32 divsel, phaseinc, auxdiv; phaseinc 5092 drivers/gpu/drm/i915/display/intel_display.c phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >> phaseinc 5101 drivers/gpu/drm/i915/display/intel_display.c desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;