phasedir         4997 drivers/gpu/drm/i915/display/intel_display.c 	u32 divsel, phaseinc, auxdiv, phasedir = 0;
phasedir         5029 drivers/gpu/drm/i915/display/intel_display.c 	WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
phasedir         5036 drivers/gpu/drm/i915/display/intel_display.c 			phasedir,
phasedir         5047 drivers/gpu/drm/i915/display/intel_display.c 	temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);