pgtbl_cfg 103 drivers/gpu/drm/panfrost/panfrost_device.h struct io_pgtable_cfg pgtbl_cfg; pgtbl_cfg 114 drivers/gpu/drm/panfrost/panfrost_mmu.c struct io_pgtable_cfg *cfg = &mmu->pgtbl_cfg; pgtbl_cfg 370 drivers/gpu/drm/panfrost/panfrost_mmu.c mmu->pgtbl_cfg = (struct io_pgtable_cfg) { pgtbl_cfg 378 drivers/gpu/drm/panfrost/panfrost_mmu.c mmu->pgtbl_ops = alloc_io_pgtable_ops(ARM_MALI_LPAE, &mmu->pgtbl_cfg, pgtbl_cfg 2154 drivers/iommu/arm-smmu-v3.c struct io_pgtable_cfg *pgtbl_cfg) pgtbl_cfg 2175 drivers/iommu/arm-smmu-v3.c cfg->cd.ttbr = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[0]; pgtbl_cfg 2176 drivers/iommu/arm-smmu-v3.c cfg->cd.tcr = pgtbl_cfg->arm_lpae_s1_cfg.tcr; pgtbl_cfg 2177 drivers/iommu/arm-smmu-v3.c cfg->cd.mair = pgtbl_cfg->arm_lpae_s1_cfg.mair[0]; pgtbl_cfg 2186 drivers/iommu/arm-smmu-v3.c struct io_pgtable_cfg *pgtbl_cfg) pgtbl_cfg 2197 drivers/iommu/arm-smmu-v3.c cfg->vttbr = pgtbl_cfg->arm_lpae_s2_cfg.vttbr; pgtbl_cfg 2198 drivers/iommu/arm-smmu-v3.c cfg->vtcr = pgtbl_cfg->arm_lpae_s2_cfg.vtcr; pgtbl_cfg 2207 drivers/iommu/arm-smmu-v3.c struct io_pgtable_cfg pgtbl_cfg; pgtbl_cfg 2244 drivers/iommu/arm-smmu-v3.c pgtbl_cfg = (struct io_pgtable_cfg) { pgtbl_cfg 2254 drivers/iommu/arm-smmu-v3.c pgtbl_cfg.quirks |= IO_PGTABLE_QUIRK_NON_STRICT; pgtbl_cfg 2256 drivers/iommu/arm-smmu-v3.c pgtbl_ops = alloc_io_pgtable_ops(fmt, &pgtbl_cfg, smmu_domain); pgtbl_cfg 2260 drivers/iommu/arm-smmu-v3.c domain->pgsize_bitmap = pgtbl_cfg.pgsize_bitmap; pgtbl_cfg 2261 drivers/iommu/arm-smmu-v3.c domain->geometry.aperture_end = (1UL << pgtbl_cfg.ias) - 1; pgtbl_cfg 2264 drivers/iommu/arm-smmu-v3.c ret = finalise_stage_fn(smmu_domain, &pgtbl_cfg); pgtbl_cfg 495 drivers/iommu/arm-smmu.c struct io_pgtable_cfg *pgtbl_cfg) pgtbl_cfg 506 drivers/iommu/arm-smmu.c cb->tcr[0] = pgtbl_cfg->arm_v7s_cfg.tcr; pgtbl_cfg 508 drivers/iommu/arm-smmu.c cb->tcr[0] = pgtbl_cfg->arm_lpae_s1_cfg.tcr; pgtbl_cfg 509 drivers/iommu/arm-smmu.c cb->tcr[1] = pgtbl_cfg->arm_lpae_s1_cfg.tcr >> 32; pgtbl_cfg 515 drivers/iommu/arm-smmu.c cb->tcr[0] = pgtbl_cfg->arm_lpae_s2_cfg.vtcr; pgtbl_cfg 521 drivers/iommu/arm-smmu.c cb->ttbr[0] = pgtbl_cfg->arm_v7s_cfg.ttbr[0]; pgtbl_cfg 522 drivers/iommu/arm-smmu.c cb->ttbr[1] = pgtbl_cfg->arm_v7s_cfg.ttbr[1]; pgtbl_cfg 524 drivers/iommu/arm-smmu.c cb->ttbr[0] = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[0]; pgtbl_cfg 526 drivers/iommu/arm-smmu.c cb->ttbr[1] = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[1]; pgtbl_cfg 530 drivers/iommu/arm-smmu.c cb->ttbr[0] = pgtbl_cfg->arm_lpae_s2_cfg.vttbr; pgtbl_cfg 536 drivers/iommu/arm-smmu.c cb->mair[0] = pgtbl_cfg->arm_v7s_cfg.prrr; pgtbl_cfg 537 drivers/iommu/arm-smmu.c cb->mair[1] = pgtbl_cfg->arm_v7s_cfg.nmrr; pgtbl_cfg 539 drivers/iommu/arm-smmu.c cb->mair[0] = pgtbl_cfg->arm_lpae_s1_cfg.mair[0]; pgtbl_cfg 540 drivers/iommu/arm-smmu.c cb->mair[1] = pgtbl_cfg->arm_lpae_s1_cfg.mair[1]; pgtbl_cfg 634 drivers/iommu/arm-smmu.c struct io_pgtable_cfg pgtbl_cfg; pgtbl_cfg 768 drivers/iommu/arm-smmu.c pgtbl_cfg = (struct io_pgtable_cfg) { pgtbl_cfg 778 drivers/iommu/arm-smmu.c pgtbl_cfg.quirks |= IO_PGTABLE_QUIRK_NON_STRICT; pgtbl_cfg 780 drivers/iommu/arm-smmu.c pgtbl_ops = alloc_io_pgtable_ops(fmt, &pgtbl_cfg, smmu_domain); pgtbl_cfg 787 drivers/iommu/arm-smmu.c domain->pgsize_bitmap = pgtbl_cfg.pgsize_bitmap; pgtbl_cfg 792 drivers/iommu/arm-smmu.c arm_smmu_init_context_bank(smmu_domain, &pgtbl_cfg); pgtbl_cfg 229 drivers/iommu/qcom_iommu.c struct io_pgtable_cfg pgtbl_cfg; pgtbl_cfg 237 drivers/iommu/qcom_iommu.c pgtbl_cfg = (struct io_pgtable_cfg) { pgtbl_cfg 246 drivers/iommu/qcom_iommu.c pgtbl_ops = alloc_io_pgtable_ops(ARM_32_LPAE_S1, &pgtbl_cfg, fwspec); pgtbl_cfg 254 drivers/iommu/qcom_iommu.c domain->pgsize_bitmap = pgtbl_cfg.pgsize_bitmap; pgtbl_cfg 255 drivers/iommu/qcom_iommu.c domain->geometry.aperture_end = (1ULL << pgtbl_cfg.ias) - 1; pgtbl_cfg 272 drivers/iommu/qcom_iommu.c pgtbl_cfg.arm_lpae_s1_cfg.ttbr[0] | pgtbl_cfg 275 drivers/iommu/qcom_iommu.c pgtbl_cfg.arm_lpae_s1_cfg.ttbr[1] | pgtbl_cfg 280 drivers/iommu/qcom_iommu.c (pgtbl_cfg.arm_lpae_s1_cfg.tcr >> 32) | pgtbl_cfg 283 drivers/iommu/qcom_iommu.c pgtbl_cfg.arm_lpae_s1_cfg.tcr); pgtbl_cfg 287 drivers/iommu/qcom_iommu.c pgtbl_cfg.arm_lpae_s1_cfg.mair[0]); pgtbl_cfg 289 drivers/iommu/qcom_iommu.c pgtbl_cfg.arm_lpae_s1_cfg.mair[1]);