pgpuobj           215 drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c nvkm_gpuobj_del(struct nvkm_gpuobj **pgpuobj)
pgpuobj           217 drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c 	struct nvkm_gpuobj *gpuobj = *pgpuobj;
pgpuobj           223 drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c 		kfree(*pgpuobj);
pgpuobj           224 drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c 		*pgpuobj = NULL;
pgpuobj           230 drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c 		struct nvkm_gpuobj *parent, struct nvkm_gpuobj **pgpuobj)
pgpuobj           235 drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c 	if (!(gpuobj = *pgpuobj = kzalloc(sizeof(*gpuobj), GFP_KERNEL)))
pgpuobj           240 drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c 		nvkm_gpuobj_del(pgpuobj);
pgpuobj           250 drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c nvkm_gpuobj_wrap(struct nvkm_memory *memory, struct nvkm_gpuobj **pgpuobj)
pgpuobj           252 drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c 	if (!(*pgpuobj = kzalloc(sizeof(**pgpuobj), GFP_KERNEL)))
pgpuobj           255 drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c 	(*pgpuobj)->addr = nvkm_memory_addr(memory);
pgpuobj           256 drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c 	(*pgpuobj)->size = nvkm_memory_size(memory);
pgpuobj           171 drivers/gpu/drm/nouveau/nvkm/core/object.c 		 int align, struct nvkm_gpuobj **pgpuobj)
pgpuobj           174 drivers/gpu/drm/nouveau/nvkm/core/object.c 		return object->func->bind(object, gpuobj, align, pgpuobj);
pgpuobj            91 drivers/gpu/drm/nouveau/nvkm/core/oproxy.c 		 int align, struct nvkm_gpuobj **pgpuobj)
pgpuobj            94 drivers/gpu/drm/nouveau/nvkm/core/oproxy.c 				parent, align, pgpuobj);
pgpuobj            35 drivers/gpu/drm/nouveau/nvkm/engine/cipher/g84.c 		       int align, struct nvkm_gpuobj **pgpuobj)
pgpuobj            38 drivers/gpu/drm/nouveau/nvkm/engine/cipher/g84.c 				  align, false, parent, pgpuobj);
pgpuobj            40 drivers/gpu/drm/nouveau/nvkm/engine/cipher/g84.c 		nvkm_kmap(*pgpuobj);
pgpuobj            41 drivers/gpu/drm/nouveau/nvkm/engine/cipher/g84.c 		nvkm_wo32(*pgpuobj, 0x00, object->oclass);
pgpuobj            42 drivers/gpu/drm/nouveau/nvkm/engine/cipher/g84.c 		nvkm_wo32(*pgpuobj, 0x04, 0x00000000);
pgpuobj            43 drivers/gpu/drm/nouveau/nvkm/engine/cipher/g84.c 		nvkm_wo32(*pgpuobj, 0x08, 0x00000000);
pgpuobj            44 drivers/gpu/drm/nouveau/nvkm/engine/cipher/g84.c 		nvkm_wo32(*pgpuobj, 0x0c, 0x00000000);
pgpuobj            45 drivers/gpu/drm/nouveau/nvkm/engine/cipher/g84.c 		nvkm_done(*pgpuobj);
pgpuobj            57 drivers/gpu/drm/nouveau/nvkm/engine/cipher/g84.c 		       int align, struct nvkm_gpuobj **pgpuobj)
pgpuobj            60 drivers/gpu/drm/nouveau/nvkm/engine/cipher/g84.c 			       align, true, parent, pgpuobj);
pgpuobj            49 drivers/gpu/drm/nouveau/nvkm/engine/dma/user.c 		 int align, struct nvkm_gpuobj **pgpuobj)
pgpuobj            52 drivers/gpu/drm/nouveau/nvkm/engine/dma/user.c 	return dmaobj->func->bind(dmaobj, gpuobj, align, pgpuobj);
pgpuobj            42 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.c 		  int align, struct nvkm_gpuobj **pgpuobj)
pgpuobj            48 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.c 	ret = nvkm_gpuobj_new(device, 24, align, false, parent, pgpuobj);
pgpuobj            50 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.c 		nvkm_kmap(*pgpuobj);
pgpuobj            51 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.c 		nvkm_wo32(*pgpuobj, 0x00, dmaobj->flags0);
pgpuobj            52 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.c 		nvkm_wo32(*pgpuobj, 0x04, lower_32_bits(dmaobj->base.limit));
pgpuobj            53 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.c 		nvkm_wo32(*pgpuobj, 0x08, lower_32_bits(dmaobj->base.start));
pgpuobj            54 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.c 		nvkm_wo32(*pgpuobj, 0x0c, upper_32_bits(dmaobj->base.limit) << 24 |
pgpuobj            56 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.c 		nvkm_wo32(*pgpuobj, 0x10, 0x00000000);
pgpuobj            57 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.c 		nvkm_wo32(*pgpuobj, 0x14, dmaobj->flags5);
pgpuobj            58 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.c 		nvkm_done(*pgpuobj);
pgpuobj            41 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf119.c 		  int align, struct nvkm_gpuobj **pgpuobj)
pgpuobj            47 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf119.c 	ret = nvkm_gpuobj_new(device, 24, align, false, parent, pgpuobj);
pgpuobj            49 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf119.c 		nvkm_kmap(*pgpuobj);
pgpuobj            50 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf119.c 		nvkm_wo32(*pgpuobj, 0x00, dmaobj->flags0);
pgpuobj            51 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf119.c 		nvkm_wo32(*pgpuobj, 0x04, dmaobj->base.start >> 8);
pgpuobj            52 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf119.c 		nvkm_wo32(*pgpuobj, 0x08, dmaobj->base.limit >> 8);
pgpuobj            53 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf119.c 		nvkm_wo32(*pgpuobj, 0x0c, 0x00000000);
pgpuobj            54 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf119.c 		nvkm_wo32(*pgpuobj, 0x10, 0x00000000);
pgpuobj            55 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf119.c 		nvkm_wo32(*pgpuobj, 0x14, 0x00000000);
pgpuobj            56 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf119.c 		nvkm_done(*pgpuobj);
pgpuobj            39 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergv100.c 		  int align, struct nvkm_gpuobj **pgpuobj)
pgpuobj            47 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergv100.c 	ret = nvkm_gpuobj_new(device, 24, align, false, parent, pgpuobj);
pgpuobj            49 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergv100.c 		nvkm_kmap(*pgpuobj);
pgpuobj            50 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergv100.c 		nvkm_wo32(*pgpuobj, 0x00, dmaobj->flags0);
pgpuobj            51 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergv100.c 		nvkm_wo32(*pgpuobj, 0x04, lower_32_bits(start));
pgpuobj            52 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergv100.c 		nvkm_wo32(*pgpuobj, 0x08, upper_32_bits(start));
pgpuobj            53 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergv100.c 		nvkm_wo32(*pgpuobj, 0x0c, lower_32_bits(limit));
pgpuobj            54 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergv100.c 		nvkm_wo32(*pgpuobj, 0x10, upper_32_bits(limit));
pgpuobj            55 drivers/gpu/drm/nouveau/nvkm/engine/dma/usergv100.c 		nvkm_done(*pgpuobj);
pgpuobj            42 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c 		 int align, struct nvkm_gpuobj **pgpuobj)
pgpuobj            55 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c 			return nvkm_gpuobj_wrap(pgt, pgpuobj);
pgpuobj            62 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c 	ret = nvkm_gpuobj_new(device, 16, align, false, parent, pgpuobj);
pgpuobj            64 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c 		nvkm_kmap(*pgpuobj);
pgpuobj            65 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c 		nvkm_wo32(*pgpuobj, 0x00, dmaobj->flags0 | (adjust << 20));
pgpuobj            66 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c 		nvkm_wo32(*pgpuobj, 0x04, length);
pgpuobj            67 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c 		nvkm_wo32(*pgpuobj, 0x08, dmaobj->flags2 | offset);
pgpuobj            68 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c 		nvkm_wo32(*pgpuobj, 0x0c, dmaobj->flags2 | offset);
pgpuobj            69 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.c 		nvkm_done(*pgpuobj);
pgpuobj            42 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c 		 int align, struct nvkm_gpuobj **pgpuobj)
pgpuobj            48 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c 	ret = nvkm_gpuobj_new(device, 24, align, false, parent, pgpuobj);
pgpuobj            50 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c 		nvkm_kmap(*pgpuobj);
pgpuobj            51 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c 		nvkm_wo32(*pgpuobj, 0x00, dmaobj->flags0);
pgpuobj            52 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c 		nvkm_wo32(*pgpuobj, 0x04, lower_32_bits(dmaobj->base.limit));
pgpuobj            53 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c 		nvkm_wo32(*pgpuobj, 0x08, lower_32_bits(dmaobj->base.start));
pgpuobj            54 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c 		nvkm_wo32(*pgpuobj, 0x0c, upper_32_bits(dmaobj->base.limit) << 24 |
pgpuobj            56 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c 		nvkm_wo32(*pgpuobj, 0x10, 0x00000000);
pgpuobj            57 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c 		nvkm_wo32(*pgpuobj, 0x14, dmaobj->flags5);
pgpuobj            58 drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.c 		nvkm_done(*pgpuobj);
pgpuobj            47 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c 			int align, struct nvkm_gpuobj **pgpuobj)
pgpuobj            50 drivers/gpu/drm/nouveau/nvkm/engine/falcon.c 			       align, true, parent, pgpuobj);
pgpuobj           321 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 		   int align, struct nvkm_gpuobj **pgpuobj)
pgpuobj           328 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 			      align, false, parent, pgpuobj);
pgpuobj           332 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 	nvkm_kmap(*pgpuobj);
pgpuobj           334 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 		nvkm_wo32(*pgpuobj, i, gr->data[i / 4]);
pgpuobj           337 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 		nvkm_wo32(*pgpuobj, 0x00, chan->mmio_nr / 2);
pgpuobj           338 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 		nvkm_wo32(*pgpuobj, 0x04, chan->mmio_vma->addr >> 8);
pgpuobj           340 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 		nvkm_wo32(*pgpuobj, 0xf4, 0);
pgpuobj           341 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 		nvkm_wo32(*pgpuobj, 0xf8, 0);
pgpuobj           342 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 		nvkm_wo32(*pgpuobj, 0x10, chan->mmio_nr / 2);
pgpuobj           343 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 		nvkm_wo32(*pgpuobj, 0x14, lower_32_bits(chan->mmio_vma->addr));
pgpuobj           344 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 		nvkm_wo32(*pgpuobj, 0x18, upper_32_bits(chan->mmio_vma->addr));
pgpuobj           345 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 		nvkm_wo32(*pgpuobj, 0x1c, 1);
pgpuobj           346 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 		nvkm_wo32(*pgpuobj, 0x20, 0);
pgpuobj           347 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 		nvkm_wo32(*pgpuobj, 0x28, 0);
pgpuobj           348 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 		nvkm_wo32(*pgpuobj, 0x2c, 0);
pgpuobj           350 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c 	nvkm_done(*pgpuobj);
pgpuobj          1044 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c 		    int align, struct nvkm_gpuobj **pgpuobj)
pgpuobj          1047 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c 				  false, parent, pgpuobj);
pgpuobj          1049 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c 		nvkm_kmap(*pgpuobj);
pgpuobj          1050 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c 		nvkm_wo32(*pgpuobj, 0x00, object->oclass);
pgpuobj          1052 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c 		nvkm_mo32(*pgpuobj, 0x00, 0x00080000, 0x00080000);
pgpuobj          1054 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c 		nvkm_wo32(*pgpuobj, 0x04, 0x00000000);
pgpuobj          1055 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c 		nvkm_wo32(*pgpuobj, 0x08, 0x00000000);
pgpuobj          1056 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c 		nvkm_wo32(*pgpuobj, 0x0c, 0x00000000);
pgpuobj          1057 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c 		nvkm_done(*pgpuobj);
pgpuobj            45 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c 		    int align, struct nvkm_gpuobj **pgpuobj)
pgpuobj            48 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c 				  false, parent, pgpuobj);
pgpuobj            50 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c 		nvkm_kmap(*pgpuobj);
pgpuobj            51 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c 		nvkm_wo32(*pgpuobj, 0x00, object->oclass);
pgpuobj            52 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c 		nvkm_wo32(*pgpuobj, 0x04, 0x00000000);
pgpuobj            53 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c 		nvkm_wo32(*pgpuobj, 0x08, 0x00000000);
pgpuobj            55 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c 		nvkm_mo32(*pgpuobj, 0x08, 0x01000000, 0x01000000);
pgpuobj            57 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c 		nvkm_wo32(*pgpuobj, 0x0c, 0x00000000);
pgpuobj            58 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c 		nvkm_wo32(*pgpuobj, 0x10, 0x00000000);
pgpuobj            59 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c 		nvkm_done(*pgpuobj);
pgpuobj            75 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c 		  int align, struct nvkm_gpuobj **pgpuobj)
pgpuobj            80 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c 				  align, true, parent, pgpuobj);
pgpuobj            82 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c 		chan->inst = (*pgpuobj)->addr;
pgpuobj            83 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c 		nvkm_kmap(*pgpuobj);
pgpuobj            84 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c 		nv40_grctx_fill(gr->base.engine.subdev.device, *pgpuobj);
pgpuobj            85 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c 		nvkm_wo32(*pgpuobj, 0x00000, chan->inst >> 4);
pgpuobj            86 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c 		nvkm_done(*pgpuobj);
pgpuobj            44 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c 		    int align, struct nvkm_gpuobj **pgpuobj)
pgpuobj            47 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c 				  align, false, parent, pgpuobj);
pgpuobj            49 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c 		nvkm_kmap(*pgpuobj);
pgpuobj            50 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c 		nvkm_wo32(*pgpuobj, 0x00, object->oclass);
pgpuobj            51 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c 		nvkm_wo32(*pgpuobj, 0x04, 0x00000000);
pgpuobj            52 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c 		nvkm_wo32(*pgpuobj, 0x08, 0x00000000);
pgpuobj            53 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c 		nvkm_wo32(*pgpuobj, 0x0c, 0x00000000);
pgpuobj            54 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c 		nvkm_done(*pgpuobj);
pgpuobj            70 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c 		  int align, struct nvkm_gpuobj **pgpuobj)
pgpuobj            74 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c 				  align, true, parent, pgpuobj);
pgpuobj            76 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c 		nvkm_kmap(*pgpuobj);
pgpuobj            77 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c 		nv50_grctx_fill(gr->base.engine.subdev.device, *pgpuobj);
pgpuobj            78 drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c 		nvkm_done(*pgpuobj);
pgpuobj            40 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c 		      int align, struct nvkm_gpuobj **pgpuobj)
pgpuobj            43 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c 				  false, parent, pgpuobj);
pgpuobj            45 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c 		nvkm_kmap(*pgpuobj);
pgpuobj            46 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c 		nvkm_wo32(*pgpuobj, 0x00, object->oclass);
pgpuobj            47 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c 		nvkm_wo32(*pgpuobj, 0x04, 0x00000000);
pgpuobj            48 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c 		nvkm_wo32(*pgpuobj, 0x08, 0x00000000);
pgpuobj            49 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c 		nvkm_wo32(*pgpuobj, 0x0c, 0x00000000);
pgpuobj            50 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.c 		nvkm_done(*pgpuobj);
pgpuobj            53 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c 		    int align, struct nvkm_gpuobj **pgpuobj)
pgpuobj            57 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c 				  align, true, parent, pgpuobj);
pgpuobj            59 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c 		chan->inst = (*pgpuobj)->addr;
pgpuobj            60 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c 		nvkm_kmap(*pgpuobj);
pgpuobj            61 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c 		nvkm_wo32(*pgpuobj, 0x78, 0x02001ec1);
pgpuobj            62 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.c 		nvkm_done(*pgpuobj);
pgpuobj            38 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv50.c 		      int align, struct nvkm_gpuobj **pgpuobj)
pgpuobj            41 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv50.c 				  align, true, parent, pgpuobj);
pgpuobj            43 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv50.c 		nvkm_kmap(*pgpuobj);
pgpuobj            44 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv50.c 		nvkm_wo32(*pgpuobj, 0x70, 0x00801ec1);
pgpuobj            45 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv50.c 		nvkm_wo32(*pgpuobj, 0x7c, 0x0000037c);
pgpuobj            46 drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv50.c 		nvkm_done(*pgpuobj);
pgpuobj            45 drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c 			int align, struct nvkm_gpuobj **pgpuobj)
pgpuobj            48 drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c 			       true, parent, pgpuobj);