pfit_control      558 drivers/gpu/drm/gma500/cdv_intel_display.c 	u32 pfit_control;
pfit_control      560 drivers/gpu/drm/gma500/cdv_intel_display.c 	pfit_control = REG_READ(PFIT_CONTROL);
pfit_control      563 drivers/gpu/drm/gma500/cdv_intel_display.c 	if ((pfit_control & PFIT_ENABLE) == 0)
pfit_control      565 drivers/gpu/drm/gma500/cdv_intel_display.c 	return (pfit_control >> 29) & 0x3;
pfit_control     1092 drivers/gpu/drm/gma500/cdv_intel_dp.c 		uint32_t pfit_control;
pfit_control     1097 drivers/gpu/drm/gma500/cdv_intel_dp.c 			pfit_control = PFIT_ENABLE;
pfit_control     1099 drivers/gpu/drm/gma500/cdv_intel_dp.c 			pfit_control = 0;
pfit_control     1101 drivers/gpu/drm/gma500/cdv_intel_dp.c 		pfit_control |= gma_crtc->pipe << PFIT_PIPE_SHIFT;
pfit_control     1103 drivers/gpu/drm/gma500/cdv_intel_dp.c 		REG_WRITE(PFIT_CONTROL, pfit_control);
pfit_control      346 drivers/gpu/drm/gma500/cdv_intel_lvds.c 	u32 pfit_control;
pfit_control      361 drivers/gpu/drm/gma500/cdv_intel_lvds.c 		pfit_control = (PFIT_ENABLE | VERT_AUTO_SCALE |
pfit_control      365 drivers/gpu/drm/gma500/cdv_intel_lvds.c 		pfit_control = 0;
pfit_control      367 drivers/gpu/drm/gma500/cdv_intel_lvds.c 	pfit_control |= gma_crtc->pipe << PFIT_PIPE_SHIFT;
pfit_control      370 drivers/gpu/drm/gma500/cdv_intel_lvds.c 		pfit_control |= PANEL_8TO6_DITHER_ENABLE;
pfit_control      372 drivers/gpu/drm/gma500/cdv_intel_lvds.c 	REG_WRITE(PFIT_CONTROL, pfit_control);
pfit_control      104 drivers/gpu/drm/gma500/mdfld_intel_display.c 	u32 pfit_control;
pfit_control      106 drivers/gpu/drm/gma500/mdfld_intel_display.c 	pfit_control = REG_READ(PFIT_CONTROL);
pfit_control      109 drivers/gpu/drm/gma500/mdfld_intel_display.c 	if ((pfit_control & PFIT_ENABLE) == 0)
pfit_control      113 drivers/gpu/drm/gma500/mdfld_intel_display.c 	return (pfit_control >> 29) & 0x3;
pfit_control      346 drivers/gpu/drm/gma500/oaktrail_crtc.c 	u32 pfit_control;
pfit_control      348 drivers/gpu/drm/gma500/oaktrail_crtc.c 	pfit_control = REG_READ(PFIT_CONTROL);
pfit_control      351 drivers/gpu/drm/gma500/oaktrail_crtc.c 	if ((pfit_control & PFIT_ENABLE) == 0)
pfit_control      353 drivers/gpu/drm/gma500/oaktrail_crtc.c 	return (pfit_control >> 29) & 3;
pfit_control       80 drivers/gpu/drm/gma500/psb_intel_display.c 	u32 pfit_control;
pfit_control       82 drivers/gpu/drm/gma500/psb_intel_display.c 	pfit_control = REG_READ(PFIT_CONTROL);
pfit_control       85 drivers/gpu/drm/gma500/psb_intel_display.c 	if ((pfit_control & PFIT_ENABLE) == 0)
pfit_control      461 drivers/gpu/drm/gma500/psb_intel_lvds.c 	u32 pfit_control;
pfit_control      476 drivers/gpu/drm/gma500/psb_intel_lvds.c 		pfit_control = (PFIT_ENABLE | VERT_AUTO_SCALE |
pfit_control      480 drivers/gpu/drm/gma500/psb_intel_lvds.c 		pfit_control = 0;
pfit_control      483 drivers/gpu/drm/gma500/psb_intel_lvds.c 		pfit_control |= PANEL_8TO6_DITHER_ENABLE;
pfit_control      485 drivers/gpu/drm/gma500/psb_intel_lvds.c 	REG_WRITE(PFIT_CONTROL, pfit_control);
pfit_control      890 drivers/gpu/drm/i915/display/intel_overlay.c 	u32 pfit_control = I915_READ(PFIT_CONTROL);
pfit_control      900 drivers/gpu/drm/i915/display/intel_overlay.c 		if (pfit_control & VERT_AUTO_SCALE)
pfit_control      301 drivers/gpu/drm/i915/display/intel_panel.c 			      u32 *pfit_control)
pfit_control      311 drivers/gpu/drm/i915/display/intel_panel.c 		*pfit_control |= PFIT_ENABLE |
pfit_control      314 drivers/gpu/drm/i915/display/intel_panel.c 		*pfit_control |= PFIT_ENABLE |
pfit_control      317 drivers/gpu/drm/i915/display/intel_panel.c 		*pfit_control |= PFIT_ENABLE | PFIT_SCALING_AUTO;
pfit_control      321 drivers/gpu/drm/i915/display/intel_panel.c 			      u32 *pfit_control, u32 *pfit_pgm_ratios,
pfit_control      348 drivers/gpu/drm/i915/display/intel_panel.c 			*pfit_control |= (PFIT_ENABLE |
pfit_control      364 drivers/gpu/drm/i915/display/intel_panel.c 			*pfit_control |= (PFIT_ENABLE |
pfit_control      370 drivers/gpu/drm/i915/display/intel_panel.c 		*pfit_control |= (PFIT_ENABLE |
pfit_control      382 drivers/gpu/drm/i915/display/intel_panel.c 	u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0;
pfit_control      403 drivers/gpu/drm/i915/display/intel_panel.c 			i965_scale_aspect(pipe_config, &pfit_control);
pfit_control      405 drivers/gpu/drm/i915/display/intel_panel.c 			i9xx_scale_aspect(pipe_config, &pfit_control,
pfit_control      415 drivers/gpu/drm/i915/display/intel_panel.c 			pfit_control |= PFIT_ENABLE;
pfit_control      417 drivers/gpu/drm/i915/display/intel_panel.c 				pfit_control |= PFIT_SCALING_AUTO;
pfit_control      419 drivers/gpu/drm/i915/display/intel_panel.c 				pfit_control |= (VERT_AUTO_SCALE |
pfit_control      433 drivers/gpu/drm/i915/display/intel_panel.c 		pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) |
pfit_control      437 drivers/gpu/drm/i915/display/intel_panel.c 	if ((pfit_control & PFIT_ENABLE) == 0) {
pfit_control      438 drivers/gpu/drm/i915/display/intel_panel.c 		pfit_control = 0;
pfit_control      444 drivers/gpu/drm/i915/display/intel_panel.c 		pfit_control |= PANEL_8TO6_DITHER_ENABLE;
pfit_control      446 drivers/gpu/drm/i915/display/intel_panel.c 	pipe_config->gmch_pfit.control = pfit_control;