pfcc_reg          426 drivers/net/ethernet/mellanox/mlx5/core/port.c 	u32 in[MLX5_ST_SZ_DW(pfcc_reg)] = {0};
pfcc_reg          428 drivers/net/ethernet/mellanox/mlx5/core/port.c 	MLX5_SET(pfcc_reg, in, local_port, 1);
pfcc_reg          436 drivers/net/ethernet/mellanox/mlx5/core/port.c 	u32 in[MLX5_ST_SZ_DW(pfcc_reg)] = {0};
pfcc_reg          437 drivers/net/ethernet/mellanox/mlx5/core/port.c 	u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
pfcc_reg          439 drivers/net/ethernet/mellanox/mlx5/core/port.c 	MLX5_SET(pfcc_reg, in, local_port, 1);
pfcc_reg          440 drivers/net/ethernet/mellanox/mlx5/core/port.c 	MLX5_SET(pfcc_reg, in, pptx, tx_pause);
pfcc_reg          441 drivers/net/ethernet/mellanox/mlx5/core/port.c 	MLX5_SET(pfcc_reg, in, pprx, rx_pause);
pfcc_reg          451 drivers/net/ethernet/mellanox/mlx5/core/port.c 	u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
pfcc_reg          459 drivers/net/ethernet/mellanox/mlx5/core/port.c 		*rx_pause = MLX5_GET(pfcc_reg, out, pprx);
pfcc_reg          462 drivers/net/ethernet/mellanox/mlx5/core/port.c 		*tx_pause = MLX5_GET(pfcc_reg, out, pptx);
pfcc_reg          472 drivers/net/ethernet/mellanox/mlx5/core/port.c 	u32 in[MLX5_ST_SZ_DW(pfcc_reg)] = {0};
pfcc_reg          473 drivers/net/ethernet/mellanox/mlx5/core/port.c 	u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
pfcc_reg          475 drivers/net/ethernet/mellanox/mlx5/core/port.c 	MLX5_SET(pfcc_reg, in, local_port, 1);
pfcc_reg          476 drivers/net/ethernet/mellanox/mlx5/core/port.c 	MLX5_SET(pfcc_reg, in, pptx_mask_n, 1);
pfcc_reg          477 drivers/net/ethernet/mellanox/mlx5/core/port.c 	MLX5_SET(pfcc_reg, in, pprx_mask_n, 1);
pfcc_reg          478 drivers/net/ethernet/mellanox/mlx5/core/port.c 	MLX5_SET(pfcc_reg, in, ppan_mask_n, 1);
pfcc_reg          479 drivers/net/ethernet/mellanox/mlx5/core/port.c 	MLX5_SET(pfcc_reg, in, critical_stall_mask, 1);
pfcc_reg          480 drivers/net/ethernet/mellanox/mlx5/core/port.c 	MLX5_SET(pfcc_reg, in, minor_stall_mask, 1);
pfcc_reg          481 drivers/net/ethernet/mellanox/mlx5/core/port.c 	MLX5_SET(pfcc_reg, in, device_stall_critical_watermark,
pfcc_reg          483 drivers/net/ethernet/mellanox/mlx5/core/port.c 	MLX5_SET(pfcc_reg, in, device_stall_minor_watermark, stall_minor_watermark);
pfcc_reg          493 drivers/net/ethernet/mellanox/mlx5/core/port.c 	u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
pfcc_reg          501 drivers/net/ethernet/mellanox/mlx5/core/port.c 		*stall_critical_watermark = MLX5_GET(pfcc_reg, out,
pfcc_reg          505 drivers/net/ethernet/mellanox/mlx5/core/port.c 		*stall_minor_watermark = MLX5_GET(pfcc_reg, out,
pfcc_reg          513 drivers/net/ethernet/mellanox/mlx5/core/port.c 	u32 in[MLX5_ST_SZ_DW(pfcc_reg)] = {0};
pfcc_reg          514 drivers/net/ethernet/mellanox/mlx5/core/port.c 	u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
pfcc_reg          516 drivers/net/ethernet/mellanox/mlx5/core/port.c 	MLX5_SET(pfcc_reg, in, local_port, 1);
pfcc_reg          517 drivers/net/ethernet/mellanox/mlx5/core/port.c 	MLX5_SET(pfcc_reg, in, pfctx, pfc_en_tx);
pfcc_reg          518 drivers/net/ethernet/mellanox/mlx5/core/port.c 	MLX5_SET(pfcc_reg, in, pfcrx, pfc_en_rx);
pfcc_reg          519 drivers/net/ethernet/mellanox/mlx5/core/port.c 	MLX5_SET_TO_ONES(pfcc_reg, in, prio_mask_tx);
pfcc_reg          520 drivers/net/ethernet/mellanox/mlx5/core/port.c 	MLX5_SET_TO_ONES(pfcc_reg, in, prio_mask_rx);
pfcc_reg          529 drivers/net/ethernet/mellanox/mlx5/core/port.c 	u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
pfcc_reg          537 drivers/net/ethernet/mellanox/mlx5/core/port.c 		*pfc_en_tx = MLX5_GET(pfcc_reg, out, pfctx);
pfcc_reg          540 drivers/net/ethernet/mellanox/mlx5/core/port.c 		*pfc_en_rx = MLX5_GET(pfcc_reg, out, pfcrx);
pfcc_reg         9455 include/linux/mlx5/mlx5_ifc.h 	struct mlx5_ifc_pfcc_reg_bits pfcc_reg;