pf_qx_ctl          39 drivers/crypto/cavium/cpt/cptpf_mbox.c 	union cptx_pf_qx_ctl pf_qx_ctl;
pf_qx_ctl          41 drivers/crypto/cavium/cpt/cptpf_mbox.c 	pf_qx_ctl.u = cpt_read_csr64(cpt->reg_base, CPTX_PF_QX_CTL(0, vf));
pf_qx_ctl          42 drivers/crypto/cavium/cpt/cptpf_mbox.c 	pf_qx_ctl.s.size = size;
pf_qx_ctl          43 drivers/crypto/cavium/cpt/cptpf_mbox.c 	pf_qx_ctl.s.cont_err = true;
pf_qx_ctl          44 drivers/crypto/cavium/cpt/cptpf_mbox.c 	cpt_write_csr64(cpt->reg_base, CPTX_PF_QX_CTL(0, vf), pf_qx_ctl.u);
pf_qx_ctl          52 drivers/crypto/cavium/cpt/cptpf_mbox.c 	union cptx_pf_qx_ctl pf_qx_ctl;
pf_qx_ctl          54 drivers/crypto/cavium/cpt/cptpf_mbox.c 	pf_qx_ctl.u = cpt_read_csr64(cpt->reg_base, CPTX_PF_QX_CTL(0, vf));
pf_qx_ctl          55 drivers/crypto/cavium/cpt/cptpf_mbox.c 	pf_qx_ctl.s.pri = pri;
pf_qx_ctl          56 drivers/crypto/cavium/cpt/cptpf_mbox.c 	cpt_write_csr64(cpt->reg_base, CPTX_PF_QX_CTL(0, vf), pf_qx_ctl.u);
pf_qx_ctl          62 drivers/crypto/cavium/cpt/cptpf_mbox.c 	union cptx_pf_qx_ctl pf_qx_ctl;
pf_qx_ctl          77 drivers/crypto/cavium/cpt/cptpf_mbox.c 	pf_qx_ctl.u = cpt_read_csr64(cpt->reg_base, CPTX_PF_QX_CTL(0, q));
pf_qx_ctl          78 drivers/crypto/cavium/cpt/cptpf_mbox.c 	pf_qx_ctl.s.grp = mcode[grp].group;
pf_qx_ctl          79 drivers/crypto/cavium/cpt/cptpf_mbox.c 	cpt_write_csr64(cpt->reg_base, CPTX_PF_QX_CTL(0, q), pf_qx_ctl.u);